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wazevo(arm64): fixes Vector select (#1839)

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Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
This commit is contained in:
Takeshi Yoneda
2023-11-15 15:26:37 +09:00
committed by GitHub
parent 0a2e2c2c51
commit ecef21ccfb
2 changed files with 2 additions and 2 deletions
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2
internal/engine/wazevo/backend/isa/arm64/lower_instr.go
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@@ -1909,7 +1909,7 @@ func (m *machine) lowerSelectVec(rc, rn, rm, rd operand) {
// First, we copy the condition to a temporary register in case rc is used somewhere else. // First, we copy the condition to a temporary register in case rc is used somewhere else.
tmp := m.compiler.AllocateVReg(ssa.TypeI32) tmp := m.compiler.AllocateVReg(ssa.TypeI32)
mov := m.allocateInstr() mov := m.allocateInstr()
mov.asFpuMov128(tmp, rc.nr()) mov.asMove32(tmp, rc.nr())
m.insert(mov) m.insert(mov)
// Next is to clear the unnecessary bits of rc by ANDing it with 1, and store it to a temporary register. // Next is to clear the unnecessary bits of rc by ANDing it with 1, and store it to a temporary register.

2
internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go
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@@ -853,7 +853,7 @@ func TestMachine_lowerSelectVec(t *testing.T) {
m.lowerSelectVec(c, rn, rm, rd) m.lowerSelectVec(c, rn, rm, rd)
require.Equal(t, ` require.Equal(t, `
mov v5?.16b, v1?.16b mov w5?, w1?
and w6?, w5?, #0x1 and w6?, w5?, #0x1
sub x7?, xzr, x6? sub x7?, xzr, x6?
dup v4?.2d, x7? dup v4?.2d, x7?