wazevo(arm64): fixes copyToTmp (#1832)

Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>

internal/engine/wazevo/backend/backend_test.go

@@ -1097,10 +1097,10 @@ L1 (SSA Block: blk0):
 	mov x8, x0
 	msr fpsr, xzr
 	fcvtzs x0, d0
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d0
+	mov v8.16b, v0.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L17)
 	fcmp d8, d8
 	mov x10, x9
@@ -1123,10 +1123,10 @@ L16:
 L17:
 	msr fpsr, xzr
 	fcvtzs x1, s1
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d1
+	mov v8.16b, v1.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L15)
 	fcmp s8, s8
 	mov x10, x9
@@ -1149,10 +1149,10 @@ L14:
 L15:
 	msr fpsr, xzr
 	fcvtzs w2, d0
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d0
+	mov v8.16b, v0.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L13)
 	fcmp d8, d8
 	mov x10, x9
@@ -1175,10 +1175,10 @@ L12:
 L13:
 	msr fpsr, xzr
 	fcvtzs w3, s1
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d1
+	mov v8.16b, v1.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L11)
 	fcmp s8, s8
 	mov x10, x9
@@ -1201,10 +1201,10 @@ L10:
 L11:
 	msr fpsr, xzr
 	fcvtzu x4, d0
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d0
+	mov v8.16b, v0.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L9)
 	fcmp d8, d8
 	mov x10, x9
@@ -1227,10 +1227,10 @@ L8:
 L9:
 	msr fpsr, xzr
 	fcvtzu x5, s1
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d1
+	mov v8.16b, v1.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L7)
 	fcmp s8, s8
 	mov x10, x9
@@ -1253,10 +1253,10 @@ L6:
 L7:
 	msr fpsr, xzr
 	fcvtzu w6, d0
-	mrs x9 fpsr
-	subs xzr, x9, #0x1
+	mrs x10 fpsr
 	mov x9, x8
-	mov d8, d0
+	mov v8.16b, v0.16b
+	subs xzr, x10, #0x1
 	b.ne #0x70, (L5)
 	fcmp d8, d8
 	mov x10, x9
@@ -1280,8 +1280,8 @@ L5:
 	msr fpsr, xzr
 	fcvtzu w7, s1
 	mrs x9 fpsr
+	mov v8.16b, v1.16b
 	subs xzr, x9, #0x1
-	mov d8, d1
 	b.ne #0x70, (L3)
 	fcmp s8, s8
 	mov x9, x8

internal/engine/wazevo/backend/isa/arm64/lower_instr.go

@@ -1311,15 +1311,15 @@ func (m *machine) lowerFpuToInt(rd, rn operand, ctx regalloc.VReg, signed, src64
 		getFlag.asMovFromFPSR(tmpReg)
 		m.insert(getFlag)
 
+		execCtx := m.copyToTmp(ctx)
+		_rn := operandNR(m.copyToTmp(rn.nr()))
+
 		// Check if the conversion was undefined by comparing the status with 1.
 		// See https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/FPSR--Floating-point-Status-Register
 		alu := m.allocateInstr()
 		alu.asALU(aluOpSubS, operandNR(xzrVReg), operandNR(tmpReg), operandImm12(1, 0), true)
 		m.insert(alu)
 
-		execCtx := m.copyToTmp(ctx)
-		_rn := operandNR(m.copyToTmp(rn.nr()))
-
 		// If it is not undefined, we can return the result.
 		ok := m.allocateInstr()
 		m.insert(ok)
@@ -1943,7 +1943,11 @@ func (m *machine) copyToTmp(v regalloc.VReg) regalloc.VReg {
 	typ := m.compiler.TypeOf(v)
 	mov := m.allocateInstr()
 	tmp := m.compiler.AllocateVReg(typ)
-	mov.asMove64(tmp, v)
+	if typ.IsInt() {
+		mov.asMove64(tmp, v)
+	} else {
+		mov.asFpuMov128(tmp, v)
+	}
 	m.insert(mov)
 	return tmp
 }

internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go

@@ -415,9 +415,9 @@ func TestMachine_lowerFpuToInt(t *testing.T) {
 msr fpsr, xzr
 fcvtzu w1, s2
 mrs x1? fpsr
-subs xzr, x1?, #0x1
 mov x2?, x15
 mov x3?, d2
+subs xzr, x1?, #0x1
 b.ne L2
 fcmp w3?, w3?
 mov x4?, x2?