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wazevo(arm64): fixes lowerVMinMaxPseudo (#1836)

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Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
This commit is contained in:
Takeshi Yoneda
2023-11-15 08:13:07 +09:00
committed by GitHub
parent 6a7e474e02
commit a1b48079b9
1 changed files with 4 additions and 9 deletions
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13
internal/engine/wazevo/backend/isa/arm64/lower_instr.go
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@@ -1108,15 +1108,9 @@ func (m *machine) lowerVMinMaxPseudo(instr *ssa.Instruction, max bool) {
rn := m.getOperand_NR(m.compiler.ValueDefinition(x), extModeNone)
rm := m.getOperand_NR(m.compiler.ValueDefinition(y), extModeNone)
creg := m.getOperand_NR(m.compiler.ValueDefinition(instr.Return()), extModeNone)
tmp := operandNR(m.compiler.AllocateVReg(ssa.TypeV128))
// creg is overwritten by BSL, so we need to move it to the result register before the instruction
// in case when it is used somewhere else.
rd := m.compiler.VRegOf(instr.Return())
mov := m.allocateInstr()
mov.asFpuMov128(tmp.nr(), creg.nr())
m.insert(mov)
// TODO: this usage of tmp is weird - it should be fine directly using rd. (seems a bug in regalloc).
tmp := operandNR(m.compiler.AllocateVReg(ssa.TypeV128))
fcmgt := m.allocateInstr()
if max {
@@ -1131,8 +1125,9 @@ func (m *machine) lowerVMinMaxPseudo(instr *ssa.Instruction, max bool) {
bsl.asVecRRR(vecOpBsl, tmp, rm, rn, vecArrangement16B)
m.insert(bsl)
res := operandNR(m.compiler.VRegOf(instr.Return()))
mov2 := m.allocateInstr()
mov2.asFpuMov128(rd, tmp.nr())
mov2.asFpuMov128(res.nr(), tmp.nr())
m.insert(mov2)
}