1962 lines
49 KiB
Go
1962 lines
49 KiB
Go
package arm64
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import (
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"fmt"
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"math"
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"strings"
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"github.com/tetratelabs/wazero/internal/engine/wazevo/backend/regalloc"
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"github.com/tetratelabs/wazero/internal/engine/wazevo/ssa"
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)
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type (
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// instruction represents either a real instruction in arm64, or the meta instructions
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// that are convenient for code generation. For example, inline constants are also treated
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// as instructions.
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//
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// Basically, each instruction knows how to get encoded in binaries. Hence, the final output of compilation
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// can be considered equivalent to the sequence of such instructions.
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//
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// Each field is interpreted depending on the kind.
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//
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// TODO: optimize the layout later once the impl settles.
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instruction struct {
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kind instructionKind
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prev, next *instruction
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u1, u2, u3 uint64
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rd, rm, rn, ra operand
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amode addressMode
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abi *abiImpl
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targets []uint32
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addedBeforeRegAlloc bool
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}
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// instructionKind represents the kind of instruction.
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// This controls how the instruction struct is interpreted.
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instructionKind int
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)
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type defKind byte
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const (
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defKindNone defKind = iota + 1
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defKindRD
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defKindCall
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)
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var defKinds = [numInstructionKinds]defKind{
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adr: defKindRD,
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aluRRR: defKindRD,
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aluRRRR: defKindRD,
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aluRRImm12: defKindRD,
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aluRRBitmaskImm: defKindRD,
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aluRRRShift: defKindRD,
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aluRRImmShift: defKindRD,
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aluRRRExtend: defKindRD,
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bitRR: defKindRD,
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movZ: defKindRD,
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movK: defKindRD,
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movN: defKindRD,
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mov32: defKindRD,
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mov64: defKindRD,
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fpuMov64: defKindRD,
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fpuMov128: defKindRD,
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fpuRR: defKindRD,
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fpuRRR: defKindRD,
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nop0: defKindNone,
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call: defKindCall,
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callInd: defKindCall,
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ret: defKindNone,
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store8: defKindNone,
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store16: defKindNone,
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store32: defKindNone,
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store64: defKindNone,
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exitSequence: defKindNone,
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condBr: defKindNone,
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br: defKindNone,
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brTableSequence: defKindNone,
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cSet: defKindRD,
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extend: defKindRD,
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fpuCmp: defKindNone,
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uLoad8: defKindRD,
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uLoad16: defKindRD,
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uLoad32: defKindRD,
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sLoad8: defKindRD,
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sLoad16: defKindRD,
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sLoad32: defKindRD,
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uLoad64: defKindRD,
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fpuLoad32: defKindRD,
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fpuLoad64: defKindRD,
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fpuLoad128: defKindRD,
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loadFpuConst32: defKindRD,
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loadFpuConst64: defKindRD,
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loadFpuConst128: defKindRD,
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fpuStore32: defKindNone,
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fpuStore64: defKindNone,
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fpuStore128: defKindNone,
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udf: defKindNone,
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cSel: defKindRD,
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fpuCSel: defKindRD,
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movToVec: defKindRD,
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movFromVec: defKindRD,
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vecMisc: defKindRD,
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vecLanes: defKindRD,
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vecRRR: defKindRD,
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fpuToInt: defKindRD,
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intToFpu: defKindRD,
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cCmpImm: defKindNone,
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movToFPSR: defKindNone,
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movFromFPSR: defKindRD,
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}
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// defs returns the list of regalloc.VReg that are defined by the instruction.
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// In order to reduce the number of allocations, the caller can pass the slice to be used.
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func (i *instruction) defs(regs []regalloc.VReg) []regalloc.VReg {
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switch defKinds[i.kind] {
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case defKindNone:
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case defKindRD:
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regs = append(regs, i.rd.nr())
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case defKindCall:
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regs = append(regs, i.abi.retRealRegs...)
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default:
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panic(fmt.Sprintf("defKind for %v not defined", i))
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}
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return regs
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}
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func (i *instruction) assignDef(reg regalloc.VReg) {
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switch defKinds[i.kind] {
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case defKindNone:
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case defKindRD:
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i.rd = i.rd.assignReg(reg)
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case defKindCall:
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panic("BUG: call instructions shouldn't be assigned")
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default:
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panic(fmt.Sprintf("defKind for %v not defined", i))
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}
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}
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type useKind byte
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const (
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useKindNone useKind = iota + 1
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useKindRN
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useKindRNRM
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useKindRNRMRA
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useKindRet
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useKindCall
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useKindCallInd
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useKindAMode
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useKindRNAMode
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useKindCond
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)
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var useKinds = [numInstructionKinds]useKind{
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udf: useKindNone,
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aluRRR: useKindRNRM,
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aluRRRR: useKindRNRMRA,
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aluRRImm12: useKindRN,
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aluRRBitmaskImm: useKindRN,
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aluRRRShift: useKindRNRM,
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aluRRImmShift: useKindRN,
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aluRRRExtend: useKindRNRM,
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bitRR: useKindRN,
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movZ: useKindNone,
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movK: useKindNone,
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movN: useKindNone,
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mov32: useKindRN,
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mov64: useKindRN,
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fpuMov64: useKindRN,
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fpuMov128: useKindRN,
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fpuRR: useKindRN,
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fpuRRR: useKindRNRM,
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nop0: useKindNone,
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call: useKindCall,
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callInd: useKindCallInd,
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ret: useKindRet,
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store8: useKindRNAMode,
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store16: useKindRNAMode,
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store32: useKindRNAMode,
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store64: useKindRNAMode,
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exitSequence: useKindRN,
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condBr: useKindCond,
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br: useKindNone,
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brTableSequence: useKindRN,
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cSet: useKindNone,
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extend: useKindRN,
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fpuCmp: useKindRNRM,
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uLoad8: useKindAMode,
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uLoad16: useKindAMode,
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uLoad32: useKindAMode,
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sLoad8: useKindAMode,
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sLoad16: useKindAMode,
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sLoad32: useKindAMode,
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uLoad64: useKindAMode,
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fpuLoad32: useKindAMode,
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fpuLoad64: useKindAMode,
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fpuLoad128: useKindAMode,
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fpuStore32: useKindRNAMode,
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fpuStore64: useKindRNAMode,
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fpuStore128: useKindRNAMode,
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loadFpuConst32: useKindNone,
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loadFpuConst64: useKindNone,
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loadFpuConst128: useKindNone,
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cSel: useKindRNRM,
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fpuCSel: useKindRNRM,
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movToVec: useKindRN,
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movFromVec: useKindRN,
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cCmpImm: useKindRN,
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vecMisc: useKindRN,
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vecLanes: useKindRN,
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vecRRR: useKindRNRM,
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fpuToInt: useKindRN,
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intToFpu: useKindRN,
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movToFPSR: useKindRN,
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movFromFPSR: useKindNone,
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adr: useKindNone,
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}
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// uses returns the list of regalloc.VReg that are used by the instruction.
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// In order to reduce the number of allocations, the caller can pass the slice to be used.
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func (i *instruction) uses(regs []regalloc.VReg) []regalloc.VReg {
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switch useKinds[i.kind] {
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case useKindNone:
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case useKindRN:
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if rn := i.rn.reg(); rn.Valid() {
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regs = append(regs, rn)
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}
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case useKindRNRM:
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if rn := i.rn.reg(); rn.Valid() {
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regs = append(regs, rn)
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}
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if rm := i.rm.reg(); rm.Valid() {
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regs = append(regs, rm)
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}
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case useKindRNRMRA:
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if rn := i.rn.reg(); rn.Valid() {
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regs = append(regs, rn)
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}
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if rm := i.rm.reg(); rm.Valid() {
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regs = append(regs, rm)
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}
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if ra := i.ra.reg(); ra.Valid() {
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regs = append(regs, ra)
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}
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case useKindRet:
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regs = append(regs, i.abi.retRealRegs...)
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case useKindAMode:
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if amodeRN := i.amode.rn; amodeRN.Valid() {
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regs = append(regs, amodeRN)
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}
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if amodeRM := i.amode.rm; amodeRM.Valid() {
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regs = append(regs, amodeRM)
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}
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case useKindRNAMode:
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regs = append(regs, i.rn.reg())
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if amodeRN := i.amode.rn; amodeRN.Valid() {
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regs = append(regs, amodeRN)
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}
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if amodeRM := i.amode.rm; amodeRM.Valid() {
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regs = append(regs, amodeRM)
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}
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case useKindCond:
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cnd := cond(i.u1)
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if cnd.kind() != condKindCondFlagSet {
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regs = append(regs, cnd.register())
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}
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case useKindCall:
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regs = append(regs, i.abi.argRealRegs...)
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case useKindCallInd:
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regs = append(regs, i.rn.nr())
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regs = append(regs, i.abi.argRealRegs...)
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default:
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panic(fmt.Sprintf("useKind for %v not defined", i))
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}
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return regs
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}
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func (i *instruction) assignUse(index int, reg regalloc.VReg) {
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switch useKinds[i.kind] {
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case useKindNone:
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case useKindRN:
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if rn := i.rn.reg(); rn.Valid() {
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i.rn = i.rn.assignReg(reg)
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}
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case useKindRNRM:
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if index == 0 {
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if rn := i.rn.reg(); rn.Valid() {
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i.rn = i.rn.assignReg(reg)
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}
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} else {
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if rm := i.rm.reg(); rm.Valid() {
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i.rm = i.rm.assignReg(reg)
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}
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}
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case useKindRNRMRA:
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if index == 0 {
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if rn := i.rn.reg(); rn.Valid() {
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i.rn = i.rn.assignReg(reg)
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}
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} else if index == 1 {
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if rm := i.rm.reg(); rm.Valid() {
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i.rm = i.rm.assignReg(reg)
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}
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} else {
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if ra := i.ra.reg(); ra.Valid() {
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i.ra = i.ra.assignReg(reg)
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}
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}
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case useKindRet:
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panic("BUG: ret instructions shouldn't be assigned")
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case useKindAMode:
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if index == 0 {
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if amodeRN := i.amode.rn; amodeRN.Valid() {
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i.amode.rn = reg
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}
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} else {
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if amodeRM := i.amode.rm; amodeRM.Valid() {
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i.amode.rm = reg
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}
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}
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case useKindRNAMode:
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if index == 0 {
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i.rn = i.rn.assignReg(reg)
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} else if index == 1 {
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if amodeRN := i.amode.rn; amodeRN.Valid() {
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i.amode.rn = reg
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}
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} else {
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if amodeRM := i.amode.rm; amodeRM.Valid() {
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i.amode.rm = reg
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}
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}
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case useKindCond:
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c := cond(i.u1)
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switch c.kind() {
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case condKindRegisterZero:
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i.u1 = uint64(registerAsRegZeroCond(reg))
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case condKindRegisterNotZero:
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i.u1 = uint64(registerAsRegNotZeroCond(reg))
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}
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case useKindCall:
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panic("BUG: call instructions shouldn't be assigned")
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case useKindCallInd:
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i.rn = i.rn.assignReg(reg)
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default:
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panic(fmt.Sprintf("useKind for %v not defined", i))
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}
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}
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func (i *instruction) asCall(ref ssa.FuncRef, abi *abiImpl) {
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i.kind = call
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i.u1 = uint64(ref)
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i.abi = abi
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}
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func (i *instruction) asCallIndirect(ptr regalloc.VReg, abi *abiImpl) {
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i.kind = callInd
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i.rn = operandNR(ptr)
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i.abi = abi
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}
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func (i *instruction) callFuncRef() ssa.FuncRef {
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return ssa.FuncRef(i.u1)
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}
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// shift must be divided by 16 and must be in range 0-3 (if dst64bit is true) or 0-1 (if dst64bit is false)
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func (i *instruction) asMOVZ(dst regalloc.VReg, imm uint64, shift uint64, dst64bit bool) {
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i.kind = movZ
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i.rd = operandNR(dst)
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i.u1 = imm
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i.u2 = shift
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if dst64bit {
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i.u3 = 1
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}
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}
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// shift must be divided by 16 and must be in range 0-3 (if dst64bit is true) or 0-1 (if dst64bit is false)
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func (i *instruction) asMOVK(dst regalloc.VReg, imm uint64, shift uint64, dst64bit bool) {
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i.kind = movK
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i.rd = operandNR(dst)
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i.u1 = imm
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i.u2 = shift
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if dst64bit {
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i.u3 = 1
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}
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}
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// shift must be divided by 16 and must be in range 0-3 (if dst64bit is true) or 0-1 (if dst64bit is false)
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func (i *instruction) asMOVN(dst regalloc.VReg, imm uint64, shift uint64, dst64bit bool) {
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i.kind = movN
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i.rd = operandNR(dst)
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i.u1 = imm
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i.u2 = shift
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if dst64bit {
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i.u3 = 1
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}
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}
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func (i *instruction) asNop0() *instruction {
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i.kind = nop0
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return i
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}
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func (i *instruction) asNop0WithLabel(l label) {
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i.kind = nop0
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i.u1 = uint64(l)
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}
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func (i *instruction) nop0Label() label {
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return label(i.u1)
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}
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func (i *instruction) asRet(abi *abiImpl) {
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i.kind = ret
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i.abi = abi
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}
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func (i *instruction) asStorePair64(src1, src2 regalloc.VReg, amode addressMode) {
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i.kind = storeP64
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i.rn = operandNR(src1)
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i.rm = operandNR(src2)
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i.amode = amode
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}
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func (i *instruction) asLoadPair64(src1, src2 regalloc.VReg, amode addressMode) {
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i.kind = loadP64
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i.rn = operandNR(src1)
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i.rm = operandNR(src2)
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i.amode = amode
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}
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func (i *instruction) asStore(src operand, amode addressMode, sizeInBits byte) {
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switch sizeInBits {
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case 8:
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i.kind = store8
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case 16:
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i.kind = store16
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case 32:
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if src.reg().RegType() == regalloc.RegTypeInt {
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i.kind = store32
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} else {
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i.kind = fpuStore32
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}
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case 64:
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if src.reg().RegType() == regalloc.RegTypeInt {
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i.kind = store64
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} else {
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i.kind = fpuStore64
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}
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case 128:
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i.kind = fpuStore128
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}
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i.rn = src
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i.amode = amode
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}
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func (i *instruction) asSLoad(dst operand, amode addressMode, sizeInBits byte) {
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switch sizeInBits {
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case 8:
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i.kind = sLoad8
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case 16:
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i.kind = sLoad16
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case 32:
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i.kind = sLoad32
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default:
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panic("BUG")
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}
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i.rd = dst
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i.amode = amode
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}
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func (i *instruction) asULoad(dst operand, amode addressMode, sizeInBits byte) {
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switch sizeInBits {
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case 8:
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i.kind = uLoad8
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case 16:
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i.kind = uLoad16
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case 32:
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i.kind = uLoad32
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case 64:
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i.kind = uLoad64
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}
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i.rd = dst
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i.amode = amode
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}
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func (i *instruction) asFpuLoad(dst operand, amode addressMode, sizeInBits byte) {
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switch sizeInBits {
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case 32:
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i.kind = fpuLoad32
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case 64:
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i.kind = fpuLoad64
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case 128:
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i.kind = fpuLoad128
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}
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i.rd = dst
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i.amode = amode
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}
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func (i *instruction) asCSet(rd regalloc.VReg, c condFlag) {
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i.kind = cSet
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i.rd = operandNR(rd)
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i.u1 = uint64(c)
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}
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func (i *instruction) asCSel(rd, rn, rm operand, c condFlag, _64bit bool) {
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i.kind = cSel
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i.rd = rd
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i.rn = rn
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i.rm = rm
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i.u1 = uint64(c)
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if _64bit {
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i.u3 = 1
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}
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}
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func (i *instruction) asFpuCSel(rd, rn, rm operand, c condFlag, _64bit bool) {
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i.kind = fpuCSel
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i.rd = rd
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i.rn = rn
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i.rm = rm
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i.u1 = uint64(c)
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if _64bit {
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i.u3 = 1
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}
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}
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func (i *instruction) asBr(target label) {
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if target == returnLabel {
|
|
panic("BUG: call site should special case for returnLabel")
|
|
}
|
|
i.kind = br
|
|
i.u1 = uint64(target)
|
|
}
|
|
|
|
func (i *instruction) asBrTableSequence(indexReg regalloc.VReg, targets []uint32) {
|
|
i.kind = brTableSequence
|
|
i.rn = operandNR(indexReg)
|
|
i.targets = targets
|
|
}
|
|
|
|
func (i *instruction) brTableSequenceOffsetsResolved() {
|
|
i.u3 = 1 // indicate that the offsets are resolved, for debugging.
|
|
}
|
|
|
|
func (i *instruction) brLabel() label {
|
|
return label(i.u1)
|
|
}
|
|
|
|
// brOffsetResolved is called when the target label is resolved.
|
|
func (i *instruction) brOffsetResolved(offset int64) {
|
|
i.u2 = uint64(offset)
|
|
i.u3 = 1 // indicate that the offset is resolved, for debugging.
|
|
}
|
|
|
|
func (i *instruction) brOffset() int64 {
|
|
return int64(i.u2)
|
|
}
|
|
|
|
// asCondBr encodes a conditional branch instruction. is64bit is only needed when cond is not flag.
|
|
func (i *instruction) asCondBr(c cond, target label, is64bit bool) {
|
|
i.kind = condBr
|
|
i.u1 = c.asUint64()
|
|
i.u2 = uint64(target)
|
|
if is64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) condBrLabel() label {
|
|
return label(i.u2)
|
|
}
|
|
|
|
// condBrOffsetResolve is called when the target label is resolved.
|
|
func (i *instruction) condBrOffsetResolve(offset int64) {
|
|
i.rd.data = uint64(offset)
|
|
i.rd.data2 = 1 // indicate that the offset is resolved, for debugging.
|
|
}
|
|
|
|
// condBrOffsetResolved returns true if condBrOffsetResolve is already called.
|
|
func (i *instruction) condBrOffsetResolved() bool {
|
|
return i.rd.data2 == 1
|
|
}
|
|
|
|
func (i *instruction) condBrOffset() int64 {
|
|
return int64(i.rd.data)
|
|
}
|
|
|
|
func (i *instruction) condBrCond() cond {
|
|
return cond(i.u1)
|
|
}
|
|
|
|
func (i *instruction) condBr64bit() bool {
|
|
return i.u3 == 1
|
|
}
|
|
|
|
func (i *instruction) asLoadFpuConst32(rd regalloc.VReg, raw uint64) {
|
|
i.kind = loadFpuConst32
|
|
i.u1 = raw
|
|
i.rd = operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asLoadFpuConst64(rd regalloc.VReg, raw uint64) {
|
|
i.kind = loadFpuConst64
|
|
i.u1 = raw
|
|
i.rd = operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asLoadFpuConst128(rd regalloc.VReg, lo, hi uint64) {
|
|
i.kind = loadFpuConst128
|
|
i.u1 = lo
|
|
i.u2 = hi
|
|
i.rd = operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asFpuCmp(rn, rm operand, is64bit bool) {
|
|
i.kind = fpuCmp
|
|
i.rn, i.rm = rn, rm
|
|
if is64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asCCmpImm(rn operand, imm uint64, c condFlag, flag byte, is64bit bool) {
|
|
i.kind = cCmpImm
|
|
i.rn = rn
|
|
i.rm.data = imm
|
|
i.u1 = uint64(c)
|
|
i.u2 = uint64(flag)
|
|
if is64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
// asALU setups a basic ALU instruction.
|
|
func (i *instruction) asALU(aluOp aluOp, rd, rn, rm operand, dst64bit bool) {
|
|
switch rm.kind {
|
|
case operandKindNR:
|
|
i.kind = aluRRR
|
|
case operandKindSR:
|
|
i.kind = aluRRRShift
|
|
case operandKindER:
|
|
i.kind = aluRRRExtend
|
|
case operandKindImm12:
|
|
i.kind = aluRRImm12
|
|
default:
|
|
panic("BUG")
|
|
}
|
|
i.u1 = uint64(aluOp)
|
|
i.rd, i.rn, i.rm = rd, rn, rm
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
// asALU setups a basic ALU instruction.
|
|
func (i *instruction) asALURRRR(aluOp aluOp, rd, rn, rm, ra operand, dst64bit bool) {
|
|
i.kind = aluRRRR
|
|
i.u1 = uint64(aluOp)
|
|
i.rd, i.rn, i.rm, i.ra = rd, rn, rm, ra
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
// asALUShift setups a shift based ALU instruction.
|
|
func (i *instruction) asALUShift(aluOp aluOp, rd, rn, rm operand, dst64bit bool) {
|
|
switch rm.kind {
|
|
case operandKindNR:
|
|
i.kind = aluRRR // If the shift amount op is a register, then the instruction is encoded as a normal ALU instruction with two register operands.
|
|
case operandKindShiftImm:
|
|
i.kind = aluRRImmShift
|
|
default:
|
|
panic("BUG")
|
|
}
|
|
i.u1 = uint64(aluOp)
|
|
i.rd, i.rn, i.rm = rd, rn, rm
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asALUBitmaskImm(aluOp aluOp, rn, rd regalloc.VReg, imm uint64, dst64bit bool) {
|
|
i.kind = aluRRBitmaskImm
|
|
i.u1 = uint64(aluOp)
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
i.u2 = imm
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asMovToFPSR(rn regalloc.VReg) {
|
|
i.kind = movToFPSR
|
|
i.rn = operandNR(rn)
|
|
}
|
|
|
|
func (i *instruction) asMovFromFPSR(rd regalloc.VReg) {
|
|
i.kind = movFromFPSR
|
|
i.rd = operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asBitRR(bitOp bitOp, rd, rn regalloc.VReg, is64bit bool) {
|
|
i.kind = bitRR
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
i.u1 = uint64(bitOp)
|
|
if is64bit {
|
|
i.u2 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asFpuRRR(op fpuBinOp, rd, rn, rm operand, dst64bit bool) {
|
|
i.kind = fpuRRR
|
|
i.u1 = uint64(op)
|
|
i.rd, i.rn, i.rm = rd, rn, rm
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asFpuRR(op fpuUniOp, rd, rn operand, dst64bit bool) {
|
|
i.kind = fpuRR
|
|
i.u1 = uint64(op)
|
|
i.rd, i.rn = rd, rn
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asExtend(rd, rn regalloc.VReg, fromBits, toBits byte, signed bool) {
|
|
i.kind = extend
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
i.u1 = uint64(fromBits)
|
|
i.u2 = uint64(toBits)
|
|
if signed {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asMove32(rd, rn regalloc.VReg) {
|
|
i.kind = mov32
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asMove64(rd, rn regalloc.VReg) {
|
|
i.kind = mov64
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asFpuMov64(rd, rn regalloc.VReg) {
|
|
i.kind = fpuMov64
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asFpuMov128(rd, rn regalloc.VReg) {
|
|
i.kind = fpuMov128
|
|
i.rn, i.rd = operandNR(rn), operandNR(rd)
|
|
}
|
|
|
|
func (i *instruction) asMovToVec(rd, rn operand, arr vecArrangement, index vecIndex) {
|
|
i.kind = movToVec
|
|
i.rd = rd
|
|
i.rn = rn
|
|
i.u1, i.u2 = uint64(arr), uint64(index)
|
|
}
|
|
|
|
func (i *instruction) asMovFromVec(rd, rn operand, arr vecArrangement, index vecIndex) {
|
|
i.kind = movFromVec
|
|
i.rd = rd
|
|
i.rn = rn
|
|
i.u1, i.u2 = uint64(arr), uint64(index)
|
|
}
|
|
|
|
func (i *instruction) asVecMisc(op vecOp, rd, rn operand, arr vecArrangement) {
|
|
i.kind = vecMisc
|
|
i.u1 = uint64(op)
|
|
i.rn, i.rd = rn, rd
|
|
i.u2 = uint64(arr)
|
|
}
|
|
|
|
func (i *instruction) asVecLanes(op vecOp, rd, rn operand, arr vecArrangement) {
|
|
i.kind = vecLanes
|
|
i.u1 = uint64(op)
|
|
i.rn, i.rd = rn, rd
|
|
i.u2 = uint64(arr)
|
|
}
|
|
|
|
func (i *instruction) asVecRRR(op vecOp, rd, rn, rm operand, arr vecArrangement) {
|
|
i.kind = vecRRR
|
|
i.u1 = uint64(op)
|
|
i.rn, i.rd, i.rm = rn, rd, rm
|
|
i.u2 = uint64(arr)
|
|
}
|
|
|
|
func (i *instruction) isCopy() bool {
|
|
op := i.kind
|
|
return op == mov64 || op == mov32 || op == fpuMov64 || op == fpuMov128
|
|
}
|
|
|
|
// String implements fmt.Stringer.
|
|
func (i *instruction) String() (str string) {
|
|
is64SizeBitToSize := func(u3 uint64) byte {
|
|
if u3 == 0 {
|
|
return 32
|
|
}
|
|
return 64
|
|
}
|
|
|
|
switch i.kind {
|
|
case nop0:
|
|
if i.u1 != 0 {
|
|
l := label(i.u1)
|
|
str = fmt.Sprintf("%s:", l)
|
|
} else {
|
|
str = "nop0"
|
|
}
|
|
case aluRRR:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s", aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size), formatVRegSized(i.rn.nr(), size),
|
|
i.rm.format(size))
|
|
case aluRRRR:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s, %s", aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size), formatVRegSized(i.rn.nr(), size), formatVRegSized(i.rm.nr(), size), formatVRegSized(i.ra.nr(), size))
|
|
case aluRRImm12:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s", aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size), formatVRegSized(i.rn.nr(), size), i.rm.format(size))
|
|
case aluRRBitmaskImm:
|
|
size := is64SizeBitToSize(i.u3)
|
|
rd, rn := formatVRegSized(i.rd.nr(), size), formatVRegSized(i.rn.nr(), size)
|
|
if size == 32 {
|
|
str = fmt.Sprintf("%s %s, %s, #%#x", aluOp(i.u1).String(), rd, rn, uint32(i.u2))
|
|
} else {
|
|
str = fmt.Sprintf("%s %s, %s, #%#x", aluOp(i.u1).String(), rd, rn, i.u2)
|
|
}
|
|
case aluRRImmShift:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %#x",
|
|
aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
i.rm.shiftImm(),
|
|
)
|
|
case aluRRRShift:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s",
|
|
aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
i.rm.format(size),
|
|
)
|
|
case aluRRRExtend:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s", aluOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
// Regardless of the source size, the register is formatted in 32-bit.
|
|
i.rm.format(32),
|
|
)
|
|
case bitRR:
|
|
size := is64SizeBitToSize(i.u2)
|
|
str = fmt.Sprintf("%s %s, %s",
|
|
bitOp(i.u1),
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
)
|
|
case uLoad8:
|
|
str = fmt.Sprintf("ldrb %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case sLoad8:
|
|
str = fmt.Sprintf("ldrsb %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case uLoad16:
|
|
str = fmt.Sprintf("ldrh %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case sLoad16:
|
|
str = fmt.Sprintf("ldrsh %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case uLoad32:
|
|
str = fmt.Sprintf("ldr %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case sLoad32:
|
|
str = fmt.Sprintf("ldrs %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case uLoad64:
|
|
str = fmt.Sprintf("ldr %s, %s", formatVRegSized(i.rd.nr(), 64), i.amode.format(64))
|
|
case store8:
|
|
str = fmt.Sprintf("strb %s, %s", formatVRegSized(i.rn.nr(), 32), i.amode.format(8))
|
|
case store16:
|
|
str = fmt.Sprintf("strh %s, %s", formatVRegSized(i.rn.nr(), 32), i.amode.format(16))
|
|
case store32:
|
|
str = fmt.Sprintf("str %s, %s", formatVRegSized(i.rn.nr(), 32), i.amode.format(32))
|
|
case store64:
|
|
str = fmt.Sprintf("str %s, %s", formatVRegSized(i.rn.nr(), 64), i.amode.format(64))
|
|
case storeP64:
|
|
str = fmt.Sprintf("stp %s, %s, %s",
|
|
formatVRegSized(i.rn.nr(), 64), formatVRegSized(i.rm.nr(), 64), i.amode.format(64))
|
|
case loadP64:
|
|
str = fmt.Sprintf("ldp %s, %s, %s",
|
|
formatVRegSized(i.rn.nr(), 64), formatVRegSized(i.rm.nr(), 64), i.amode.format(64))
|
|
case mov64:
|
|
str = fmt.Sprintf("mov %s, %s",
|
|
formatVRegSized(i.rd.nr(), 64),
|
|
formatVRegSized(i.rn.nr(), 64))
|
|
case mov32:
|
|
str = fmt.Sprintf("mov %s, %s", formatVRegSized(i.rd.nr(), 32), formatVRegSized(i.rn.nr(), 32))
|
|
case movZ:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("movz %s, #%#x, lsl %d", formatVRegSized(i.rd.nr(), size), uint16(i.u1), i.u2*16)
|
|
case movN:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("movn %s, #%#x, lsl %d", formatVRegSized(i.rd.nr(), size), uint16(i.u1), i.u2*16)
|
|
case movK:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("movk %s, #%#x, lsl %d", formatVRegSized(i.rd.nr(), size), uint16(i.u1), i.u2*16)
|
|
case extend:
|
|
fromBits, toBits := byte(i.u1), byte(i.u2)
|
|
|
|
var signedStr string
|
|
if i.u3 == 1 {
|
|
signedStr = "s"
|
|
} else {
|
|
signedStr = "u"
|
|
}
|
|
var fromStr string
|
|
switch fromBits {
|
|
case 8:
|
|
fromStr = "b"
|
|
case 16:
|
|
fromStr = "h"
|
|
case 32:
|
|
fromStr = "w"
|
|
}
|
|
str = fmt.Sprintf("%sxt%s %s, %s", signedStr, fromStr, formatVRegSized(i.rd.nr(), toBits), formatVRegSized(i.rn.nr(), 32))
|
|
case cSel:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("csel %s, %s, %s, %s",
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
formatVRegSized(i.rm.nr(), size),
|
|
condFlag(i.u1),
|
|
)
|
|
case cSet:
|
|
str = fmt.Sprintf("cset %s, %s", formatVRegSized(i.rd.nr(), 64), condFlag(i.u1))
|
|
case cCmpImm:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("ccmp %s, #%#x, #%#x, %s",
|
|
formatVRegSized(i.rn.nr(), size), i.rm.data,
|
|
i.u2&0b1111,
|
|
condFlag(i.u1))
|
|
case fpuMov64:
|
|
str = fmt.Sprintf("mov %s, %s",
|
|
formatVRegVec(i.rd.nr(), vecArrangement8B, vecIndexNone),
|
|
formatVRegVec(i.rn.nr(), vecArrangement8B, vecIndexNone))
|
|
case fpuMov128:
|
|
str = fmt.Sprintf("mov %s, %s",
|
|
formatVRegVec(i.rd.nr(), vecArrangement16B, vecIndexNone),
|
|
formatVRegVec(i.rn.nr(), vecArrangement16B, vecIndexNone))
|
|
case fpuMovFromVec:
|
|
panic("TODO")
|
|
case fpuRR:
|
|
dstSz := is64SizeBitToSize(i.u3)
|
|
srcSz := dstSz
|
|
op := fpuUniOp(i.u1)
|
|
switch op {
|
|
case fpuUniOpCvt32To64:
|
|
srcSz = 32
|
|
case fpuUniOpCvt64To32:
|
|
srcSz = 64
|
|
}
|
|
str = fmt.Sprintf("%s %s, %s", op.String(),
|
|
formatVRegSized(i.rd.nr(), dstSz), formatVRegSized(i.rn.nr(), srcSz))
|
|
case fpuRRR:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("%s %s, %s, %s", fpuBinOp(i.u1).String(),
|
|
formatVRegSized(i.rd.nr(), size), formatVRegSized(i.rn.nr(), size), formatVRegSized(i.rm.nr(), size))
|
|
case fpuRRI:
|
|
panic("TODO")
|
|
case fpuRRRR:
|
|
panic("TODO")
|
|
case fpuCmp:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("fcmp %s, %s",
|
|
formatVRegSized(i.rn.nr(), size), formatVRegSized(i.rm.nr(), size))
|
|
case fpuLoad32:
|
|
str = fmt.Sprintf("ldr %s, %s", formatVRegSized(i.rd.nr(), 32), i.amode.format(32))
|
|
case fpuStore32:
|
|
str = fmt.Sprintf("str %s, %s", formatVRegSized(i.rn.nr(), 32), i.amode.format(64))
|
|
case fpuLoad64:
|
|
str = fmt.Sprintf("ldr %s, %s", formatVRegSized(i.rd.nr(), 64), i.amode.format(64))
|
|
case fpuStore64:
|
|
str = fmt.Sprintf("str %s, %s", formatVRegSized(i.rn.nr(), 64), i.amode.format(64))
|
|
case fpuLoad128:
|
|
str = fmt.Sprintf("ldr %s, %s", formatVRegSized(i.rd.nr(), 128), i.amode.format(64))
|
|
case fpuStore128:
|
|
str = fmt.Sprintf("str %s, %s", formatVRegSized(i.rn.nr(), 128), i.amode.format(64))
|
|
case loadFpuConst32:
|
|
str = fmt.Sprintf("ldr %s, #8; b 8; data.f32 %f", formatVRegSized(i.rd.nr(), 32), math.Float32frombits(uint32(i.u1)))
|
|
case loadFpuConst64:
|
|
str = fmt.Sprintf("ldr %s, #8; b 16; data.f64 %f", formatVRegSized(i.rd.nr(), 64), math.Float64frombits(i.u1))
|
|
case loadFpuConst128:
|
|
str = fmt.Sprintf("ldr %s, #8; b 32; data.v128 %016x %016x",
|
|
formatVRegSized(i.rd.nr(), 128), i.u1, i.u2)
|
|
case fpuToInt:
|
|
var op, src, dst string
|
|
if signed := i.u1 == 1; signed {
|
|
op = "fcvtzs"
|
|
} else {
|
|
op = "fcvtzu"
|
|
}
|
|
if src64 := i.u2 == 1; src64 {
|
|
src = formatVRegWidthVec(i.rn.nr(), vecArrangementD)
|
|
} else {
|
|
src = formatVRegWidthVec(i.rn.nr(), vecArrangementS)
|
|
}
|
|
if dst64 := i.u3 == 1; dst64 {
|
|
dst = formatVRegSized(i.rd.nr(), 64)
|
|
} else {
|
|
dst = formatVRegSized(i.rd.nr(), 32)
|
|
}
|
|
str = fmt.Sprintf("%s %s, %s", op, dst, src)
|
|
|
|
case intToFpu:
|
|
var op, src, dst string
|
|
if signed := i.u1 == 1; signed {
|
|
op = "scvtf"
|
|
} else {
|
|
op = "ucvtf"
|
|
}
|
|
if src64 := i.u2 == 1; src64 {
|
|
src = formatVRegSized(i.rn.nr(), 64)
|
|
} else {
|
|
src = formatVRegSized(i.rn.nr(), 32)
|
|
}
|
|
if dst64 := i.u3 == 1; dst64 {
|
|
dst = formatVRegWidthVec(i.rd.nr(), vecArrangementD)
|
|
} else {
|
|
dst = formatVRegWidthVec(i.rd.nr(), vecArrangementS)
|
|
}
|
|
str = fmt.Sprintf("%s %s, %s", op, dst, src)
|
|
case fpuCSel:
|
|
size := is64SizeBitToSize(i.u3)
|
|
str = fmt.Sprintf("fcsel %s, %s, %s, %s",
|
|
formatVRegSized(i.rd.nr(), size),
|
|
formatVRegSized(i.rn.nr(), size),
|
|
formatVRegSized(i.rm.nr(), size),
|
|
condFlag(i.u1),
|
|
)
|
|
case movToVec:
|
|
var size byte
|
|
arr := vecArrangement(i.u1)
|
|
switch arr {
|
|
case vecArrangementB, vecArrangementH, vecArrangementS:
|
|
size = 32
|
|
case vecArrangementD:
|
|
size = 64
|
|
default:
|
|
panic("unsupported arrangement " + arr.String())
|
|
}
|
|
str = fmt.Sprintf("ins %s, %s", formatVRegVec(i.rd.nr(), arr, vecIndex(i.u2)), formatVRegSized(i.rn.nr(), size))
|
|
case movFromVec:
|
|
var size byte
|
|
var opcode string
|
|
arr := vecArrangement(i.u1)
|
|
switch arr {
|
|
case vecArrangementB, vecArrangementH, vecArrangementS:
|
|
size = 32
|
|
opcode = "umov"
|
|
case vecArrangementD:
|
|
size = 64
|
|
opcode = "mov"
|
|
default:
|
|
panic("unsupported arrangement " + arr.String())
|
|
}
|
|
str = fmt.Sprintf("%s %s, %s", opcode, formatVRegSized(i.rd.nr(), size), formatVRegVec(i.rn.nr(), arr, vecIndex(i.u2)))
|
|
case movFromVecSigned:
|
|
panic("TODO")
|
|
case vecDup:
|
|
panic("TODO")
|
|
case vecDupFromFpu:
|
|
panic("TODO")
|
|
case vecExtend:
|
|
panic("TODO")
|
|
case vecMovElement:
|
|
panic("TODO")
|
|
case vecMiscNarrow:
|
|
panic("TODO")
|
|
case vecRRR:
|
|
str = fmt.Sprintf("%s %s, %s, %s",
|
|
vecOp(i.u1),
|
|
formatVRegVec(i.rd.nr(), vecArrangement(i.u2), vecIndexNone),
|
|
formatVRegVec(i.rn.nr(), vecArrangement(i.u2), vecIndexNone),
|
|
formatVRegVec(i.rm.nr(), vecArrangement(i.u2), vecIndexNone),
|
|
)
|
|
case vecMisc:
|
|
str = fmt.Sprintf("%s %s, %s",
|
|
vecOp(i.u1),
|
|
formatVRegVec(i.rd.nr(), vecArrangement(i.u2), vecIndexNone),
|
|
formatVRegVec(i.rn.nr(), vecArrangement(i.u2), vecIndexNone))
|
|
case vecLanes:
|
|
arr := vecArrangement(i.u2)
|
|
var destArr vecArrangement
|
|
switch arr {
|
|
case vecArrangement8B, vecArrangement16B:
|
|
destArr = vecArrangementH
|
|
case vecArrangement4H, vecArrangement8H:
|
|
destArr = vecArrangementS
|
|
case vecArrangement4S:
|
|
destArr = vecArrangementD
|
|
default:
|
|
panic("invalid arrangement " + arr.String())
|
|
}
|
|
str = fmt.Sprintf("%s %s, %s",
|
|
vecOp(i.u1),
|
|
formatVRegWidthVec(i.rd.nr(), destArr),
|
|
formatVRegVec(i.rn.nr(), arr, vecIndexNone))
|
|
case vecTbl:
|
|
panic("TODO")
|
|
case vecTbl2:
|
|
panic("TODO")
|
|
case movToFPSR:
|
|
str = fmt.Sprintf("msr fpsr, %s", formatVRegSized(i.rn.nr(), 64))
|
|
case movFromFPSR:
|
|
str = fmt.Sprintf("mrs %s fpsr", formatVRegSized(i.rd.nr(), 64))
|
|
case call:
|
|
if i.u2 > 0 {
|
|
str = fmt.Sprintf("bl #%#x", i.u2)
|
|
} else {
|
|
str = fmt.Sprintf("bl %s", ssa.FuncRef(i.u1))
|
|
}
|
|
case callInd:
|
|
str = fmt.Sprintf("bl %s", formatVRegSized(i.rn.nr(), 64))
|
|
case ret:
|
|
str = "ret"
|
|
case br:
|
|
target := label(i.u1)
|
|
if i.u3 != 0 {
|
|
str = fmt.Sprintf("b #%#x (%s)", i.brOffset(), target.String())
|
|
} else {
|
|
str = fmt.Sprintf("b %s", target.String())
|
|
}
|
|
case condBr:
|
|
size := is64SizeBitToSize(i.u3)
|
|
c := cond(i.u1)
|
|
target := label(i.u2)
|
|
switch c.kind() {
|
|
case condKindRegisterZero:
|
|
if !i.condBrOffsetResolved() {
|
|
str = fmt.Sprintf("cbz %s, (%s)", formatVRegSized(c.register(), size), target.String())
|
|
} else {
|
|
str = fmt.Sprintf("cbz %s, #%#x %s", formatVRegSized(c.register(), size), i.condBrOffset(), target.String())
|
|
}
|
|
case condKindRegisterNotZero:
|
|
if offset := i.condBrOffset(); offset != 0 {
|
|
str = fmt.Sprintf("cbnz %s, #%#x (%s)", formatVRegSized(c.register(), size), offset, target.String())
|
|
} else {
|
|
str = fmt.Sprintf("cbnz %s, %s", formatVRegSized(c.register(), size), target.String())
|
|
}
|
|
case condKindCondFlagSet:
|
|
if offset := i.condBrOffset(); offset != 0 {
|
|
if target == invalidLabel {
|
|
str = fmt.Sprintf("b.%s #%#x", c.flag(), offset)
|
|
} else {
|
|
str = fmt.Sprintf("b.%s #%#x, (%s)", c.flag(), offset, target.String())
|
|
}
|
|
} else {
|
|
str = fmt.Sprintf("b.%s %s", c.flag(), target.String())
|
|
}
|
|
}
|
|
case adr:
|
|
str = fmt.Sprintf("adr %s, #%#x", formatVRegSized(i.rd.nr(), 64), int64(i.u1))
|
|
case brTableSequence:
|
|
if i.u3 == 0 { // The offsets haven't been resolved yet.
|
|
labels := make([]string, len(i.targets))
|
|
for index, l := range i.targets {
|
|
labels[index] = label(l).String()
|
|
}
|
|
str = fmt.Sprintf("br_table_sequence %s, [%s]",
|
|
formatVRegSized(i.rn.nr(), 64),
|
|
strings.Join(labels, ", "),
|
|
)
|
|
} else {
|
|
// See encodeBrTableSequence for the encoding.
|
|
offsets := make([]string, len(i.targets))
|
|
for index, offset := range i.targets {
|
|
offsets[index] = fmt.Sprintf("%#x", int32(offset))
|
|
}
|
|
str = fmt.Sprintf(
|
|
`adr %[2]s, #16; ldrsw %[1]s, [%[2]s, %[1]s, UXTW 2]; add %[2]s, %[2]s, %[1]s; br %[2]s; %s`,
|
|
formatVRegSized(i.rn.nr(), 64),
|
|
formatVRegSized(tmpRegVReg, 64),
|
|
offsets,
|
|
)
|
|
}
|
|
case exitSequence:
|
|
str = fmt.Sprintf("exit_sequence %s", formatVRegSized(i.rn.nr(), 64))
|
|
case udf:
|
|
str = "udf"
|
|
default:
|
|
panic(i.kind)
|
|
}
|
|
return
|
|
}
|
|
|
|
func (i *instruction) asAdr(rd regalloc.VReg, offset int64) {
|
|
i.kind = adr
|
|
i.rd = operandNR(rd)
|
|
i.u1 = uint64(offset)
|
|
}
|
|
|
|
// TODO: delete unnecessary things.
|
|
const (
|
|
// nop0 represents a no-op of zero size.
|
|
nop0 instructionKind = iota + 1
|
|
// aluRRR represents an ALU operation with two register sources and a register destination.
|
|
aluRRR
|
|
// aluRRRR represents an ALU operation with three register sources and a register destination.
|
|
aluRRRR
|
|
// aluRRImm12 represents an ALU operation with a register source and an immediate-12 source, with a register destination.
|
|
aluRRImm12
|
|
// aluRRBitmaskImm represents an ALU operation with a register source and a bitmask immediate, with a register destination.
|
|
aluRRBitmaskImm
|
|
// aluRRImmShift represents an ALU operation with a register source and an immediate-shifted source, with a register destination.
|
|
aluRRImmShift
|
|
// aluRRRShift represents an ALU operation with two register sources, one of which can be shifted, with a register destination.
|
|
aluRRRShift
|
|
// aluRRRExtend represents an ALU operation with two register sources, one of which can be extended, with a register destination.
|
|
aluRRRExtend
|
|
// bitRR represents a bit op instruction with a single register source.
|
|
bitRR
|
|
// uLoad8 represents an unsigned 8-bit load.
|
|
uLoad8
|
|
// sLoad8 represents a signed 8-bit load into 64-bit register.
|
|
sLoad8
|
|
// uLoad16 represents an unsigned 16-bit load into 64-bit register.
|
|
uLoad16
|
|
// sLoad16 represents a signed 16-bit load into 64-bit register.
|
|
sLoad16
|
|
// uLoad32 represents an unsigned 32-bit load into 64-bit register.
|
|
uLoad32
|
|
// sLoad32 represents a signed 32-bit load into 64-bit register.
|
|
sLoad32
|
|
// uLoad64 represents a 64-bit load.
|
|
uLoad64
|
|
// store8 represents an 8-bit store.
|
|
store8
|
|
// store16 represents a 16-bit store.
|
|
store16
|
|
// store32 represents a 32-bit store.
|
|
store32
|
|
// store64 represents a 64-bit store.
|
|
store64
|
|
// storeP64 represents a store of a pair of registers.
|
|
storeP64
|
|
// loadP64 represents a load of a pair of registers.
|
|
loadP64
|
|
// mov64 represents a MOV instruction. These are encoded as ORR's but we keep them separate for better handling.
|
|
mov64
|
|
// mov32 represents a 32-bit MOV. This zeroes the top 32 bits of the destination.
|
|
mov32
|
|
// movZ represents a MOVZ with a 16-bit immediate.
|
|
movZ
|
|
// movN represents a MOVN with a 16-bit immediate.
|
|
movN
|
|
// movK represents a MOVK with a 16-bit immediate.
|
|
movK
|
|
// extend represents a sign- or zero-extend operation.
|
|
extend
|
|
// cSel represents a conditional-select operation.
|
|
cSel
|
|
// cSet represents a conditional-set operation.
|
|
cSet
|
|
// cCmpImm represents a conditional comparison with an immediate.
|
|
cCmpImm
|
|
// fpuMov64 represents a FPU move. Distinct from a vector-register move; moving just 64 bits appears to be significantly faster.
|
|
fpuMov64
|
|
// fpuMov128 represents a vector register move.
|
|
fpuMov128
|
|
// fpuMovFromVec represents a move to scalar from a vector element.
|
|
fpuMovFromVec
|
|
// fpuRR represents a 1-op FPU instruction.
|
|
fpuRR
|
|
// fpuRRR represents a 2-op FPU instruction.
|
|
fpuRRR
|
|
// fpuRRI represents a 2-op FPU instruction with immediate value.
|
|
fpuRRI
|
|
// fpuRRRR represents a 3-op FPU instruction.
|
|
fpuRRRR
|
|
// fpuCmp represents a FPU comparison, either 32 or 64 bit.
|
|
fpuCmp
|
|
// fpuLoad32 represents a floating-point load, single-precision (32 bit).
|
|
fpuLoad32
|
|
// fpuStore32 represents a floating-point store, single-precision (32 bit).
|
|
fpuStore32
|
|
// fpuLoad64 represents a floating-point load, double-precision (64 bit).
|
|
fpuLoad64
|
|
// fpuStore64 represents a floating-point store, double-precision (64 bit).
|
|
fpuStore64
|
|
// fpuLoad128 represents a floating-point/vector load, 128 bit.
|
|
fpuLoad128
|
|
// fpuStore128 represents a floating-point/vector store, 128 bit.
|
|
fpuStore128
|
|
// loadFpuConst32 represents a load of a 32-bit floating-point constant.
|
|
loadFpuConst32
|
|
// loadFpuConst64 represents a load of a 64-bit floating-point constant.
|
|
loadFpuConst64
|
|
// loadFpuConst128 represents a load of a 128-bit floating-point constant.
|
|
loadFpuConst128
|
|
// fpuToInt represents a conversion from FP to integer.
|
|
fpuToInt
|
|
// intToFpu represents a conversion from integer to FP.
|
|
intToFpu
|
|
// fpuCSel represents a 32/64-bit FP conditional select.
|
|
fpuCSel
|
|
// movToVec represents a move to a vector element from a GPR.
|
|
movToVec
|
|
// movFromVec represents an unsigned move from a vector element to a GPR.
|
|
movFromVec
|
|
// movFromVecSigned represents a signed move from a vector element to a GPR.
|
|
movFromVecSigned
|
|
// vecDup represents a duplication of general-purpose register to vector.
|
|
vecDup
|
|
// vecDupFromFpu represents a duplication of scalar to vector.
|
|
vecDupFromFpu
|
|
// vecExtend represents a vector extension operation.
|
|
vecExtend
|
|
// vecMovElement represents a move vector element to another vector element operation.
|
|
vecMovElement
|
|
// vecMiscNarrow represents a vector narrowing operation.
|
|
vecMiscNarrow
|
|
// vecRRR represents a vector ALU operation.
|
|
vecRRR
|
|
// vecMisc represents a vector two register miscellaneous instruction.
|
|
vecMisc
|
|
// vecLanes represents a vector instruction across lanes.
|
|
vecLanes
|
|
// vecTbl represents a table vector lookup - single register table.
|
|
vecTbl
|
|
// vecTbl2 represents a table vector lookup - two register table.
|
|
vecTbl2
|
|
// movToNZCV represents a move to the FPSR.
|
|
movToFPSR
|
|
// movFromNZCV represents a move from the FPSR.
|
|
movFromFPSR
|
|
// call represents a machine call instruction.
|
|
call
|
|
// callInd represents a machine indirect-call instruction.
|
|
callInd
|
|
// ret represents a machine return instruction.
|
|
ret
|
|
// br represents an unconditional branch.
|
|
br
|
|
// condBr represents a conditional branch.
|
|
condBr
|
|
// adr represents a compute the address (using a PC-relative offset) of a memory location.
|
|
adr
|
|
// brTableSequence represents a jump-table sequence.
|
|
brTableSequence
|
|
// exitSequence consists of multiple instructions, and exits the execution immediately.
|
|
// See encodeExitSequence.
|
|
exitSequence
|
|
// UDF is the undefined instruction. For debugging only.
|
|
udf
|
|
|
|
// ------------------- do not define below this line -------------------
|
|
numInstructionKinds
|
|
)
|
|
|
|
func (i *instruction) asUDF() *instruction {
|
|
i.kind = udf
|
|
return i
|
|
}
|
|
|
|
func (i *instruction) asFpuToInt(rd, rn operand, rdSigned, src64bit, dst64bit bool) {
|
|
i.kind = fpuToInt
|
|
i.rn = rn
|
|
i.rd = rd
|
|
if rdSigned {
|
|
i.u1 = 1
|
|
}
|
|
if src64bit {
|
|
i.u2 = 1
|
|
}
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asIntToFpu(rd, rn operand, rnSigned, src64bit, dst64bit bool) {
|
|
i.kind = intToFpu
|
|
i.rn = rn
|
|
i.rd = rd
|
|
if rnSigned {
|
|
i.u1 = 1
|
|
}
|
|
if src64bit {
|
|
i.u2 = 1
|
|
}
|
|
if dst64bit {
|
|
i.u3 = 1
|
|
}
|
|
}
|
|
|
|
func (i *instruction) asExitSequence(ctx regalloc.VReg) *instruction {
|
|
i.kind = exitSequence
|
|
i.rn = operandNR(ctx)
|
|
return i
|
|
}
|
|
|
|
// aluOp determines the type of ALU operation. Instructions whose kind is one of
|
|
// aluRRR, aluRRRR, aluRRImm12, aluRRBitmaskImm, aluRRImmShift, aluRRRShift and aluRRRExtend
|
|
// would use this type.
|
|
type aluOp int
|
|
|
|
func (a aluOp) String() string {
|
|
switch a {
|
|
case aluOpAdd:
|
|
return "add"
|
|
case aluOpSub:
|
|
return "sub"
|
|
case aluOpOrr:
|
|
return "orr"
|
|
case aluOpAnd:
|
|
return "and"
|
|
case aluOpBic:
|
|
return "bic"
|
|
case aluOpEor:
|
|
return "eor"
|
|
case aluOpAddS:
|
|
return "adds"
|
|
case aluOpSubS:
|
|
return "subs"
|
|
case aluOpSMulH:
|
|
return "sMulH"
|
|
case aluOpUMulH:
|
|
return "uMulH"
|
|
case aluOpSDiv:
|
|
return "sdiv"
|
|
case aluOpUDiv:
|
|
return "udiv"
|
|
case aluOpRotR:
|
|
return "ror"
|
|
case aluOpLsr:
|
|
return "lsr"
|
|
case aluOpAsr:
|
|
return "asr"
|
|
case aluOpLsl:
|
|
return "lsl"
|
|
case aluOpMAdd:
|
|
return "madd"
|
|
case aluOpMSub:
|
|
return "msub"
|
|
}
|
|
panic(int(a))
|
|
}
|
|
|
|
const (
|
|
// 32/64-bit Add.
|
|
aluOpAdd aluOp = iota
|
|
// 32/64-bit Subtract.
|
|
aluOpSub
|
|
// 32/64-bit Bitwise OR.
|
|
aluOpOrr
|
|
// 32/64-bit Bitwise AND.
|
|
aluOpAnd
|
|
// 32/64-bit Bitwise AND NOT.
|
|
aluOpBic
|
|
// 32/64-bit Bitwise XOR (Exclusive OR).
|
|
aluOpEor
|
|
// 32/64-bit Add setting flags.
|
|
aluOpAddS
|
|
// 32/64-bit Subtract setting flags.
|
|
aluOpSubS
|
|
// Signed multiply, high-word result.
|
|
aluOpSMulH
|
|
// Unsigned multiply, high-word result.
|
|
aluOpUMulH
|
|
// 64-bit Signed divide.
|
|
aluOpSDiv
|
|
// 64-bit Unsigned divide.
|
|
aluOpUDiv
|
|
// 32/64-bit Rotate right.
|
|
aluOpRotR
|
|
// 32/64-bit Logical shift right.
|
|
aluOpLsr
|
|
// 32/64-bit Arithmetic shift right.
|
|
aluOpAsr
|
|
// 32/64-bit Logical shift left.
|
|
aluOpLsl /// Multiply-add
|
|
|
|
// MAdd and MSub are only applicable for aluRRRR.
|
|
aluOpMAdd
|
|
aluOpMSub
|
|
)
|
|
|
|
// vecOp determines the type of vector operation. Instructions whose kind is one of
|
|
// vecOpCnt would use this type.
|
|
type vecOp int
|
|
|
|
// String implements fmt.Stringer.
|
|
func (b vecOp) String() string {
|
|
switch b {
|
|
case vecOpCnt:
|
|
return "cnt"
|
|
case vecOpUaddlv:
|
|
return "uaddlv"
|
|
case vecOpBit:
|
|
return "bit"
|
|
case vecOpBic:
|
|
return "bic"
|
|
case vecOpBsl:
|
|
return "bsl"
|
|
case vecOpNot:
|
|
return "not"
|
|
case vecOpAnd:
|
|
return "and"
|
|
case vecOpOrr:
|
|
return "orr"
|
|
case vecOpEOR:
|
|
return "eor"
|
|
case vecOpAdd:
|
|
return "add"
|
|
case vecOpAddp:
|
|
return "addp"
|
|
case vecOpSub:
|
|
return "sub"
|
|
case vecOpSmin:
|
|
return "smin"
|
|
case vecOpUmin:
|
|
return "umin"
|
|
case vecOpSmax:
|
|
return "smax"
|
|
case vecOpUmax:
|
|
return "umax"
|
|
case vecOpUrhadd:
|
|
return "urhadd"
|
|
case vecOpMul:
|
|
return "mul"
|
|
case vecOpUmlal:
|
|
return "umlal"
|
|
case vecOpNeg:
|
|
return "neg"
|
|
case vecOpRev64:
|
|
return "rev64"
|
|
case vecOpXtn:
|
|
return "xtn"
|
|
case vecOpShll:
|
|
return "shll"
|
|
}
|
|
panic(int(b))
|
|
}
|
|
|
|
const (
|
|
vecOpCnt vecOp = iota
|
|
vecOpUaddlv
|
|
vecOpBit
|
|
vecOpBic
|
|
vecOpBsl
|
|
vecOpNot
|
|
vecOpAnd
|
|
vecOpOrr
|
|
vecOpEOR
|
|
vecOpAdd
|
|
vecOpSqadd
|
|
vecOpUqadd
|
|
vecOpAddp
|
|
vecOpSub
|
|
vecOpSqsub
|
|
vecOpUqsub
|
|
vecOpSmin
|
|
vecOpUmin
|
|
vecOpSmax
|
|
vecOpUmax
|
|
vecOpUmaxp
|
|
vecOpUrhadd
|
|
vecOpMul
|
|
vecOpUmlal
|
|
vecOpAbs
|
|
vecOpNeg
|
|
vecOpRev64
|
|
vecOpXtn
|
|
vecOpShll
|
|
)
|
|
|
|
// bitOp determines the type of bitwise operation. Instructions whose kind is one of
|
|
// bitOpRbit and bitOpClz would use this type.
|
|
type bitOp int
|
|
|
|
// String implements fmt.Stringer.
|
|
func (b bitOp) String() string {
|
|
switch b {
|
|
case bitOpRbit:
|
|
return "rbit"
|
|
case bitOpClz:
|
|
return "clz"
|
|
}
|
|
panic(int(b))
|
|
}
|
|
|
|
const (
|
|
// 32/64-bit Rbit.
|
|
bitOpRbit bitOp = iota
|
|
// 32/64-bit Clz.
|
|
bitOpClz
|
|
)
|
|
|
|
// fpuUniOp represents a unary floating-point unit (FPU) operation.
|
|
type fpuUniOp byte
|
|
|
|
const (
|
|
fpuUniOpNeg fpuUniOp = iota
|
|
fpuUniOpCvt32To64
|
|
fpuUniOpCvt64To32
|
|
fpuUniOpSqrt
|
|
fpuUniOpRoundPlus
|
|
fpuUniOpRoundMinus
|
|
fpuUniOpRoundZero
|
|
fpuUniOpRoundNearest
|
|
fpuUniOpAbs
|
|
)
|
|
|
|
// String implements the fmt.Stringer.
|
|
func (f fpuUniOp) String() string {
|
|
switch f {
|
|
case fpuUniOpNeg:
|
|
return "fneg"
|
|
case fpuUniOpCvt32To64:
|
|
return "fcvt"
|
|
case fpuUniOpCvt64To32:
|
|
return "fcvt"
|
|
case fpuUniOpSqrt:
|
|
return "fsqrt"
|
|
case fpuUniOpRoundPlus:
|
|
return "frintp"
|
|
case fpuUniOpRoundMinus:
|
|
return "frintm"
|
|
case fpuUniOpRoundZero:
|
|
return "frintz"
|
|
case fpuUniOpRoundNearest:
|
|
return "frintn"
|
|
case fpuUniOpAbs:
|
|
return "fabs"
|
|
}
|
|
panic(int(f))
|
|
}
|
|
|
|
// fpuBinOp represents a binary floating-point unit (FPU) operation.
|
|
type fpuBinOp byte
|
|
|
|
const (
|
|
fpuBinOpAdd = iota
|
|
fpuBinOpSub
|
|
fpuBinOpMul
|
|
fpuBinOpDiv
|
|
fpuBinOpMax
|
|
fpuBinOpMin
|
|
)
|
|
|
|
// String implements the fmt.Stringer.
|
|
func (f fpuBinOp) String() string {
|
|
switch f {
|
|
case fpuBinOpAdd:
|
|
return "fadd"
|
|
case fpuBinOpSub:
|
|
return "fsub"
|
|
case fpuBinOpMul:
|
|
return "fmul"
|
|
case fpuBinOpDiv:
|
|
return "fdiv"
|
|
case fpuBinOpMax:
|
|
return "fmax"
|
|
case fpuBinOpMin:
|
|
return "fmin"
|
|
}
|
|
panic(int(f))
|
|
}
|
|
|
|
// extMode represents the mode of a register operand extension.
|
|
// For example, aluRRRExtend instructions need this info to determine the extensions.
|
|
type extMode byte
|
|
|
|
const (
|
|
extModeNone extMode = iota
|
|
// extModeZeroExtend64 suggests a zero-extension to 32 bits if the original bit size is less than 32.
|
|
extModeZeroExtend32
|
|
// extModeSignExtend64 stands for a sign-extension to 32 bits if the original bit size is less than 32.
|
|
extModeSignExtend32
|
|
// extModeZeroExtend64 suggests a zero-extension to 64 bits if the original bit size is less than 64.
|
|
extModeZeroExtend64
|
|
// extModeSignExtend64 stands for a sign-extension to 64 bits if the original bit size is less than 64.
|
|
extModeSignExtend64
|
|
)
|
|
|
|
func (e extMode) bits() byte {
|
|
switch e {
|
|
case extModeZeroExtend32, extModeSignExtend32:
|
|
return 32
|
|
case extModeZeroExtend64, extModeSignExtend64:
|
|
return 64
|
|
default:
|
|
return 0
|
|
}
|
|
}
|
|
|
|
func (e extMode) signed() bool {
|
|
switch e {
|
|
case extModeSignExtend32, extModeSignExtend64:
|
|
return true
|
|
default:
|
|
return false
|
|
}
|
|
}
|
|
|
|
func extModeOf(t ssa.Type, signed bool) extMode {
|
|
switch t.Bits() {
|
|
case 32:
|
|
if signed {
|
|
return extModeSignExtend32
|
|
}
|
|
return extModeZeroExtend32
|
|
case 64:
|
|
if signed {
|
|
return extModeSignExtend64
|
|
}
|
|
return extModeZeroExtend64
|
|
default:
|
|
panic("TODO? do we need narrower than 32 bits?")
|
|
}
|
|
}
|
|
|
|
type extendOp byte
|
|
|
|
const (
|
|
extendOpUXTB extendOp = 0b000
|
|
extendOpUXTH extendOp = 0b001
|
|
extendOpUXTW extendOp = 0b010
|
|
// extendOpUXTX does nothing, but convenient symbol that officially exists. See:
|
|
// https://stackoverflow.com/questions/72041372/what-do-the-uxtx-and-sxtx-extensions-mean-for-32-bit-aarch64-adds-instruct
|
|
extendOpUXTX extendOp = 0b011
|
|
extendOpSXTB extendOp = 0b100
|
|
extendOpSXTH extendOp = 0b101
|
|
extendOpSXTW extendOp = 0b110
|
|
// extendOpSXTX does nothing, but convenient symbol that officially exists. See:
|
|
// https://stackoverflow.com/questions/72041372/what-do-the-uxtx-and-sxtx-extensions-mean-for-32-bit-aarch64-adds-instruct
|
|
extendOpSXTX extendOp = 0b111
|
|
extendOpNone extendOp = 0xff
|
|
)
|
|
|
|
func (e extendOp) srcBits() byte {
|
|
switch e {
|
|
case extendOpUXTB, extendOpSXTB:
|
|
return 8
|
|
case extendOpUXTH, extendOpSXTH:
|
|
return 16
|
|
case extendOpUXTW, extendOpSXTW:
|
|
return 32
|
|
case extendOpUXTX, extendOpSXTX:
|
|
return 64
|
|
}
|
|
panic(int(e))
|
|
}
|
|
|
|
func (e extendOp) String() string {
|
|
switch e {
|
|
case extendOpUXTB:
|
|
return "UXTB"
|
|
case extendOpUXTH:
|
|
return "UXTH"
|
|
case extendOpUXTW:
|
|
return "UXTW"
|
|
case extendOpUXTX:
|
|
return "UXTX"
|
|
case extendOpSXTB:
|
|
return "SXTB"
|
|
case extendOpSXTH:
|
|
return "SXTH"
|
|
case extendOpSXTW:
|
|
return "SXTW"
|
|
case extendOpSXTX:
|
|
return "SXTX"
|
|
}
|
|
panic(int(e))
|
|
}
|
|
|
|
func extendOpFrom(signed bool, from byte) extendOp {
|
|
switch from {
|
|
case 8:
|
|
if signed {
|
|
return extendOpSXTB
|
|
}
|
|
return extendOpUXTB
|
|
case 16:
|
|
if signed {
|
|
return extendOpSXTH
|
|
}
|
|
return extendOpUXTH
|
|
case 32:
|
|
if signed {
|
|
return extendOpSXTW
|
|
}
|
|
return extendOpUXTW
|
|
case 64:
|
|
if signed {
|
|
return extendOpSXTX
|
|
}
|
|
return extendOpUXTX
|
|
}
|
|
panic("invalid extendOpFrom")
|
|
}
|
|
|
|
type shiftOp byte
|
|
|
|
const (
|
|
shiftOpLSL shiftOp = 0b00
|
|
shiftOpLSR shiftOp = 0b01
|
|
shiftOpASR shiftOp = 0b10
|
|
shiftOpROR shiftOp = 0b11
|
|
)
|
|
|
|
func (s shiftOp) String() string {
|
|
switch s {
|
|
case shiftOpLSL:
|
|
return "lsl"
|
|
case shiftOpLSR:
|
|
return "lsr"
|
|
case shiftOpASR:
|
|
return "asr"
|
|
case shiftOpROR:
|
|
return "ror"
|
|
}
|
|
panic(int(s))
|
|
}
|
|
|
|
const exitSequenceSize = 6 * 4 // 6 instructions as in encodeExitSequence.
|
|
|
|
// size returns the size of the instruction in encoded bytes.
|
|
func (i *instruction) size() int64 {
|
|
switch i.kind {
|
|
case exitSequence:
|
|
return exitSequenceSize // 5 instructions as in encodeExitSequence.
|
|
case nop0:
|
|
return 0
|
|
case loadFpuConst32:
|
|
if i.u1 == 0 {
|
|
return 4 // zero loading can be encoded as a single instruction.
|
|
}
|
|
return 4 + 4 + 4
|
|
case loadFpuConst64:
|
|
if i.u1 == 0 {
|
|
return 4 // zero loading can be encoded as a single instruction.
|
|
}
|
|
return 4 + 4 + 8
|
|
case loadFpuConst128:
|
|
if i.u1 == 0 && i.u2 == 0 {
|
|
return 4 // zero loading can be encoded as a single instruction.
|
|
}
|
|
return 4 + 4 + 16
|
|
case brTableSequence:
|
|
return 4*4 + int64(len(i.targets))*4
|
|
default:
|
|
return 4
|
|
}
|
|
}
|
|
|
|
// vecArrangement is the arrangement of data within a vector register.
|
|
type vecArrangement byte
|
|
|
|
const (
|
|
// vecArrangementNone is an arrangement indicating no data is stored.
|
|
vecArrangementNone vecArrangement = iota
|
|
// vecArrangement8B is an arrangement of 8 bytes (64-bit vector)
|
|
vecArrangement8B
|
|
// vecArrangement16B is an arrangement of 16 bytes (128-bit vector)
|
|
vecArrangement16B
|
|
// vecArrangement4H is an arrangement of 4 half precisions (64-bit vector)
|
|
vecArrangement4H
|
|
// vecArrangement8H is an arrangement of 8 half precisions (128-bit vector)
|
|
vecArrangement8H
|
|
// vecArrangement2S is an arrangement of 2 single precisions (64-bit vector)
|
|
vecArrangement2S
|
|
// vecArrangement4S is an arrangement of 4 single precisions (128-bit vector)
|
|
vecArrangement4S
|
|
// vecArrangement1D is an arrangement of 1 double precision (64-bit vector)
|
|
vecArrangement1D
|
|
// vecArrangement2D is an arrangement of 2 double precisions (128-bit vector)
|
|
vecArrangement2D
|
|
|
|
// Assign each vector size specifier to a vector arrangement ID.
|
|
// Instructions can only have an arrangement or a size specifier, but not both, so it
|
|
// simplifies the internal representation of vector instructions by being able to
|
|
// store either into the same field.
|
|
|
|
// vecArrangementB is a size specifier of byte
|
|
vecArrangementB
|
|
// vecArrangementH is a size specifier of word (16-bit)
|
|
vecArrangementH
|
|
// vecArrangementS is a size specifier of double word (32-bit)
|
|
vecArrangementS
|
|
// vecArrangementD is a size specifier of quad word (64-bit)
|
|
vecArrangementD
|
|
// vecArrangementQ is a size specifier of the entire vector (128-bit)
|
|
vecArrangementQ
|
|
)
|
|
|
|
// String implements fmt.Stringer
|
|
func (v vecArrangement) String() (ret string) {
|
|
switch v {
|
|
case vecArrangement8B:
|
|
ret = "8B"
|
|
case vecArrangement16B:
|
|
ret = "16B"
|
|
case vecArrangement4H:
|
|
ret = "4H"
|
|
case vecArrangement8H:
|
|
ret = "8H"
|
|
case vecArrangement2S:
|
|
ret = "2S"
|
|
case vecArrangement4S:
|
|
ret = "4S"
|
|
case vecArrangement1D:
|
|
ret = "1D"
|
|
case vecArrangement2D:
|
|
ret = "2D"
|
|
case vecArrangementB:
|
|
ret = "B"
|
|
case vecArrangementH:
|
|
ret = "H"
|
|
case vecArrangementS:
|
|
ret = "S"
|
|
case vecArrangementD:
|
|
ret = "D"
|
|
case vecArrangementQ:
|
|
ret = "Q"
|
|
case vecArrangementNone:
|
|
ret = "none"
|
|
default:
|
|
panic(v)
|
|
}
|
|
return
|
|
}
|
|
|
|
// vecIndex is the index of an element of a vector register
|
|
type vecIndex byte
|
|
|
|
// vecIndexNone indicates no vector index specified.
|
|
const vecIndexNone = ^vecIndex(0)
|
|
|
|
func ssaLaneToArrangement(lane ssa.VecLane) vecArrangement {
|
|
switch lane {
|
|
case ssa.VecLaneI8x16:
|
|
return vecArrangement16B
|
|
case ssa.VecLaneI16x8:
|
|
return vecArrangement8H
|
|
case ssa.VecLaneI32x4:
|
|
return vecArrangement4S
|
|
case ssa.VecLaneI64x2:
|
|
return vecArrangement2D
|
|
case ssa.VecLaneF32x4:
|
|
return vecArrangement4S
|
|
case ssa.VecLaneF64x2:
|
|
return vecArrangement2D
|
|
default:
|
|
panic(lane)
|
|
}
|
|
}
|