9780f0f4a0
Signed-off-by: Achille Roussel <achille.roussel@gmail.com> Co-authored-by: Crypt Keeper <64215+codefromthecrypt@users.noreply.github.com>
1482 lines
166 KiB
Go
1482 lines
166 KiB
Go
package amd64
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import (
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"math"
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"testing"
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"github.com/tetratelabs/wazero/internal/asm"
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"github.com/tetratelabs/wazero/internal/testing/require"
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)
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func TestAssemblerImpl_encodeConstToRegister(t *testing.T) {
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t.Run("error", func(t *testing.T) {
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tests := []struct {
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n *nodeImpl
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expErr string
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}{
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{
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n: &nodeImpl{instruction: RET, types: operandTypesConstToRegister, dstReg: RegAX},
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expErr: "RET is unsupported for ConstToRegister type",
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},
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{
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n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister},
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expErr: "PSLLD needs float register but got nil",
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},
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{
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n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister, dstReg: RegAX},
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expErr: "PSLLD needs float register but got AX",
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},
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{
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n: &nodeImpl{instruction: ADDQ, types: operandTypesConstToRegister, dstReg: RegX0},
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expErr: "ADDQ needs int register but got X0",
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},
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{
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n: &nodeImpl{instruction: PSLLD, types: operandTypesConstToRegister, dstReg: RegX0, srcConst: 2199023255552},
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expErr: "constant must fit in 32-bit integer for PSLLD, but got 2199023255552",
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},
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{
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n: &nodeImpl{instruction: SHLQ, types: operandTypesConstToRegister, dstReg: RegR10, srcConst: 32768},
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expErr: "constant must fit in positive 8-bit integer for SHLQ, but got 32768",
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},
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{
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n: &nodeImpl{instruction: PSRLQ, types: operandTypesConstToRegister, dstReg: RegX0, srcConst: 32768},
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expErr: "constant must fit in signed 8-bit integer for PSRLQ, but got 32768",
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},
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}
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code := asm.CodeSegment{}
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defer func() { require.NoError(t, code.Unmap()) }()
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for _, tc := range tests {
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a := NewAssembler()
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buf := code.NextCodeSection()
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err := a.encodeConstToRegister(buf, tc.n)
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require.EqualError(t, err, tc.expErr)
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}
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})
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tests := []struct {
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name string
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c int64
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inst asm.Instruction
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dstReg asm.Register
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exp []byte
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}{
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{name: "ADDQ/c=0/dst=BX", inst: ADDQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0x0}},
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{name: "ADDQ/c=1/dst=BX", inst: ADDQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0x1}},
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{name: "ADDQ/c=-1/dst=BX", inst: ADDQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xff}},
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{name: "ADDQ/c=11/dst=BX", inst: ADDQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xb}},
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{name: "ADDQ/c=-11/dst=BX", inst: ADDQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xc3, 0xf5}},
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{name: "ADDQ/c=1243/dst=BX", inst: ADDQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xdb, 0x4, 0x0, 0x0}},
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{name: "ADDQ/c=-1234/dst=BX", inst: ADDQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "ADDQ/c=255/dst=BX", inst: ADDQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0x0, 0x0, 0x0}},
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{name: "ADDQ/c=2147483647/dst=BX", inst: ADDQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0xff, 0xff, 0x7f}},
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{name: "ADDQ/c=-2147483648/dst=BX", inst: ADDQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x0, 0x0, 0x0, 0x80}},
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{name: "ADDQ/c=32767/dst=BX", inst: ADDQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0x7f, 0x0, 0x0}},
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{name: "ADDQ/c=4294967295/dst=BX", inst: ADDQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0xff, 0xff, 0xff, 0xff}},
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{name: "ADDQ/c=-32768/dst=BX", inst: ADDQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xc3, 0x0, 0x80, 0xff, 0xff}},
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{name: "ADDQ/c=0/dst=R15", inst: ADDQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0x0}},
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{name: "ADDQ/c=1/dst=R15", inst: ADDQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0x1}},
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{name: "ADDQ/c=-1/dst=R15", inst: ADDQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xff}},
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{name: "ADDQ/c=11/dst=R15", inst: ADDQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xb}},
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{name: "ADDQ/c=-11/dst=R15", inst: ADDQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xc7, 0xf5}},
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{name: "ADDQ/c=1243/dst=R15", inst: ADDQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xdb, 0x4, 0x0, 0x0}},
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{name: "ADDQ/c=-1234/dst=R15", inst: ADDQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "ADDQ/c=255/dst=R15", inst: ADDQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0x0, 0x0, 0x0}},
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{name: "ADDQ/c=2147483647/dst=R15", inst: ADDQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0xff, 0xff, 0x7f}},
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{name: "ADDQ/c=-2147483648/dst=R15", inst: ADDQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x0, 0x0, 0x0, 0x80}},
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{name: "ADDQ/c=32767/dst=R15", inst: ADDQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0x7f, 0x0, 0x0}},
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{name: "ADDQ/c=4294967295/dst=R15", inst: ADDQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0xff, 0xff, 0xff, 0xff}},
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{name: "ADDQ/c=-32768/dst=R15", inst: ADDQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xc7, 0x0, 0x80, 0xff, 0xff}},
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{name: "ANDQ/c=0/dst=BX", inst: ANDQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0x0}},
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{name: "ANDQ/c=1/dst=BX", inst: ANDQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0x1}},
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{name: "ANDQ/c=-1/dst=BX", inst: ANDQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xff}},
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{name: "ANDQ/c=11/dst=BX", inst: ANDQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xb}},
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{name: "ANDQ/c=-11/dst=BX", inst: ANDQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xe3, 0xf5}},
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{name: "ANDQ/c=1243/dst=BX", inst: ANDQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xdb, 0x4, 0x0, 0x0}},
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{name: "ANDQ/c=-1234/dst=BX", inst: ANDQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "ANDQ/c=255/dst=BX", inst: ANDQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0x0, 0x0, 0x0}},
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{name: "ANDQ/c=2147483647/dst=BX", inst: ANDQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0xff, 0xff, 0x7f}},
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{name: "ANDQ/c=-2147483648/dst=BX", inst: ANDQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x0, 0x0, 0x0, 0x80}},
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{name: "ANDQ/c=32767/dst=BX", inst: ANDQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0x7f, 0x0, 0x0}},
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{name: "ANDQ/c=4294967295/dst=BX", inst: ANDQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0xff, 0xff, 0xff, 0xff}},
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{name: "ANDQ/c=-32768/dst=BX", inst: ANDQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xe3, 0x0, 0x80, 0xff, 0xff}},
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{name: "ANDQ/c=0/dst=R15", inst: ANDQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0x0}},
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{name: "ANDQ/c=1/dst=R15", inst: ANDQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0x1}},
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{name: "ANDQ/c=-1/dst=R15", inst: ANDQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xff}},
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{name: "ANDQ/c=11/dst=R15", inst: ANDQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xb}},
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{name: "ANDQ/c=-11/dst=R15", inst: ANDQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xe7, 0xf5}},
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{name: "ANDQ/c=1243/dst=R15", inst: ANDQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xdb, 0x4, 0x0, 0x0}},
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{name: "ANDQ/c=-1234/dst=R15", inst: ANDQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "ANDQ/c=255/dst=R15", inst: ANDQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0x0, 0x0, 0x0}},
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{name: "ANDQ/c=2147483647/dst=R15", inst: ANDQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0xff, 0xff, 0x7f}},
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{name: "ANDQ/c=-2147483648/dst=R15", inst: ANDQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x0, 0x0, 0x0, 0x80}},
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{name: "ANDQ/c=32767/dst=R15", inst: ANDQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0x7f, 0x0, 0x0}},
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{name: "ANDQ/c=4294967295/dst=R15", inst: ANDQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0xff, 0xff, 0xff, 0xff}},
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{name: "ANDQ/c=-32768/dst=R15", inst: ANDQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xe7, 0x0, 0x80, 0xff, 0xff}},
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{name: "MOVL/c=0/dst=BX", inst: MOVL, c: 0x0, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=1/dst=BX", inst: MOVL, c: 0x1, dstReg: RegBX, exp: []byte{0xbb, 0x1, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=-1/dst=BX", inst: MOVL, c: -0x1, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=11/dst=BX", inst: MOVL, c: 0xb, dstReg: RegBX, exp: []byte{0xbb, 0xb, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=-11/dst=BX", inst: MOVL, c: -0xb, dstReg: RegBX, exp: []byte{0xbb, 0xf5, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=1243/dst=BX", inst: MOVL, c: 0x4db, dstReg: RegBX, exp: []byte{0xbb, 0xdb, 0x4, 0x0, 0x0}},
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{name: "MOVL/c=-1234/dst=BX", inst: MOVL, c: -0x4d2, dstReg: RegBX, exp: []byte{0xbb, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "MOVL/c=255/dst=BX", inst: MOVL, c: 0xff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=2147483647/dst=BX", inst: MOVL, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0x7f}},
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{name: "MOVL/c=-2147483648/dst=BX", inst: MOVL, c: -0x80000000, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x0, 0x0, 0x80}},
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{name: "MOVL/c=32767/dst=BX", inst: MOVL, c: 0x7fff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0x7f, 0x0, 0x0}},
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{name: "MOVL/c=4294967295/dst=BX", inst: MOVL, c: 0xffffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=-32768/dst=BX", inst: MOVL, c: -0x8000, dstReg: RegBX, exp: []byte{0xbb, 0x0, 0x80, 0xff, 0xff}},
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{name: "MOVL/c=0/dst=R15", inst: MOVL, c: 0x0, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=1/dst=R15", inst: MOVL, c: 0x1, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x1, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=-1/dst=R15", inst: MOVL, c: -0x1, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=11/dst=R15", inst: MOVL, c: 0xb, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xb, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=-11/dst=R15", inst: MOVL, c: -0xb, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xf5, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=1243/dst=R15", inst: MOVL, c: 0x4db, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xdb, 0x4, 0x0, 0x0}},
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{name: "MOVL/c=-1234/dst=R15", inst: MOVL, c: -0x4d2, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "MOVL/c=255/dst=R15", inst: MOVL, c: 0xff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0x0, 0x0, 0x0}},
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{name: "MOVL/c=2147483647/dst=R15", inst: MOVL, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0x7f}},
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{name: "MOVL/c=-2147483648/dst=R15", inst: MOVL, c: -0x80000000, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x0, 0x0, 0x80}},
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{name: "MOVL/c=32767/dst=R15", inst: MOVL, c: 0x7fff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0x7f, 0x0, 0x0}},
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{name: "MOVL/c=4294967295/dst=R15", inst: MOVL, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVL/c=-32768/dst=R15", inst: MOVL, c: -0x8000, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0x0, 0x80, 0xff, 0xff}},
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{name: "MOVQ/c=0/dst=BX", inst: MOVQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=1/dst=BX", inst: MOVQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x1, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=-1/dst=BX", inst: MOVQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVQ/c=11/dst=BX", inst: MOVQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xb, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=-11/dst=BX", inst: MOVQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xf5, 0xff, 0xff, 0xff}},
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{name: "MOVQ/c=1243/dst=BX", inst: MOVQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xdb, 0x4, 0x0, 0x0}},
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{name: "MOVQ/c=-1234/dst=BX", inst: MOVQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x2e, 0xfb, 0xff, 0xff}},
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{name: "MOVQ/c=255/dst=BX", inst: MOVQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=2147483647/dst=BX", inst: MOVQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0xff, 0xff, 0x7f}},
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{name: "MOVQ/c=-2147483648/dst=BX", inst: MOVQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x0, 0x0, 0x80}},
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{name: "MOVQ/c=32767/dst=BX", inst: MOVQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0xff, 0x7f, 0x0, 0x0}},
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{name: "MOVQ/c=4294967295/dst=BX", inst: MOVQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0xbb, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVQ/c=-32768/dst=BX", inst: MOVQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0xc7, 0xc3, 0x0, 0x80, 0xff, 0xff}},
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{name: "MOVQ/c=9223372036854775807/dst=BX", inst: MOVQ, c: 0x7fffffffffffffff, dstReg: RegBX, exp: []byte{0x48, 0xbb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}},
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{name: "MOVQ/c=-9223372036854775808/dst=BX", inst: MOVQ, c: -0x8000000000000000, dstReg: RegBX, exp: []byte{0x48, 0xbb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}},
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{name: "MOVQ/c=0/dst=R15", inst: MOVQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=1/dst=R15", inst: MOVQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x1, 0x0, 0x0, 0x0}},
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{name: "MOVQ/c=-1/dst=R15", inst: MOVQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0xff, 0xff, 0xff}},
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{name: "MOVQ/c=11/dst=R15", inst: MOVQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xb, 0x0, 0x0, 0x0}},
|
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{name: "MOVQ/c=-11/dst=R15", inst: MOVQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xf5, 0xff, 0xff, 0xff}},
|
|
{name: "MOVQ/c=1243/dst=R15", inst: MOVQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "MOVQ/c=-1234/dst=R15", inst: MOVQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "MOVQ/c=255/dst=R15", inst: MOVQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0x0, 0x0, 0x0}},
|
|
{name: "MOVQ/c=2147483647/dst=R15", inst: MOVQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "MOVQ/c=-2147483648/dst=R15", inst: MOVQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "MOVQ/c=32767/dst=R15", inst: MOVQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "MOVQ/c=4294967295/dst=R15", inst: MOVQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0xbf, 0xff, 0xff, 0xff, 0xff}},
|
|
{name: "MOVQ/c=-32768/dst=R15", inst: MOVQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0xc7, 0xc7, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "MOVQ/c=9223372036854775807/dst=R15", inst: MOVQ, c: 0x7fffffffffffffff, dstReg: RegR15, exp: []byte{0x49, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "MOVQ/c=-9223372036854775808/dst=R15", inst: MOVQ, c: -0x8000000000000000, dstReg: RegR15, exp: []byte{0x49, 0xbf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "SHLQ/c=0/dst=BX", inst: SHLQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0x0}},
|
|
{name: "SHLQ/c=1/dst=BX", inst: SHLQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xd1, 0xe3}},
|
|
{name: "SHLQ/c=11/dst=BX", inst: SHLQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0xb}},
|
|
{name: "SHLQ/c=255/dst=BX", inst: SHLQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xe3, 0xff}},
|
|
{name: "SHLQ/c=0/dst=R15", inst: SHLQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0x0}},
|
|
{name: "SHLQ/c=1/dst=R15", inst: SHLQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xd1, 0xe7}},
|
|
{name: "SHLQ/c=11/dst=R15", inst: SHLQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0xb}},
|
|
{name: "SHLQ/c=255/dst=R15", inst: SHLQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xe7, 0xff}},
|
|
{name: "SHRQ/c=0/dst=BX", inst: SHRQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0x0}},
|
|
{name: "SHRQ/c=1/dst=BX", inst: SHRQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0xd1, 0xeb}},
|
|
{name: "SHRQ/c=11/dst=BX", inst: SHRQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0xb}},
|
|
{name: "SHRQ/c=255/dst=BX", inst: SHRQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0xc1, 0xeb, 0xff}},
|
|
{name: "SHRQ/c=0/dst=R15", inst: SHRQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0x0}},
|
|
{name: "SHRQ/c=1/dst=R15", inst: SHRQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0xd1, 0xef}},
|
|
{name: "SHRQ/c=11/dst=R15", inst: SHRQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0xb}},
|
|
{name: "SHRQ/c=255/dst=R15", inst: SHRQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0xc1, 0xef, 0xff}},
|
|
{name: "XORL/c=0/dst=BX", inst: XORL, c: 0x0, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0x0}},
|
|
{name: "XORL/c=1/dst=BX", inst: XORL, c: 0x1, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0x1}},
|
|
{name: "XORL/c=-1/dst=BX", inst: XORL, c: -0x1, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xff}},
|
|
{name: "XORL/c=11/dst=BX", inst: XORL, c: 0xb, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xb}},
|
|
{name: "XORL/c=-11/dst=BX", inst: XORL, c: -0xb, dstReg: RegBX, exp: []byte{0x83, 0xf3, 0xf5}},
|
|
{name: "XORL/c=1243/dst=BX", inst: XORL, c: 0x4db, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "XORL/c=-1234/dst=BX", inst: XORL, c: -0x4d2, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "XORL/c=255/dst=BX", inst: XORL, c: 0xff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0x0, 0x0, 0x0}},
|
|
{name: "XORL/c=2147483647/dst=BX", inst: XORL, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "XORL/c=-2147483648/dst=BX", inst: XORL, c: -0x80000000, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "XORL/c=32767/dst=BX", inst: XORL, c: 0x7fff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "XORL/c=4294967295/dst=BX", inst: XORL, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0xff, 0xff, 0xff, 0xff}},
|
|
{name: "XORL/c=-32768/dst=BX", inst: XORL, c: -0x8000, dstReg: RegBX, exp: []byte{0x81, 0xf3, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "XORL/c=0/dst=R15", inst: XORL, c: 0x0, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0x0}},
|
|
{name: "XORL/c=1/dst=R15", inst: XORL, c: 0x1, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0x1}},
|
|
{name: "XORL/c=-1/dst=R15", inst: XORL, c: -0x1, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xff}},
|
|
{name: "XORL/c=11/dst=R15", inst: XORL, c: 0xb, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xb}},
|
|
{name: "XORL/c=-11/dst=R15", inst: XORL, c: -0xb, dstReg: RegR15, exp: []byte{0x41, 0x83, 0xf7, 0xf5}},
|
|
{name: "XORL/c=1243/dst=R15", inst: XORL, c: 0x4db, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "XORL/c=-1234/dst=R15", inst: XORL, c: -0x4d2, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "XORL/c=255/dst=R15", inst: XORL, c: 0xff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0x0, 0x0, 0x0}},
|
|
{name: "XORL/c=2147483647/dst=R15", inst: XORL, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "XORL/c=-2147483648/dst=R15", inst: XORL, c: -0x80000000, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "XORL/c=32767/dst=R15", inst: XORL, c: 0x7fff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "XORL/c=4294967295/dst=R15", inst: XORL, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0xff, 0xff, 0xff, 0xff}},
|
|
{name: "XORL/c=-32768/dst=R15", inst: XORL, c: -0x8000, dstReg: RegR15, exp: []byte{0x41, 0x81, 0xf7, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "XORQ/c=0/dst=BX", inst: XORQ, c: 0x0, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0x0}},
|
|
{name: "XORQ/c=1/dst=BX", inst: XORQ, c: 0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0x1}},
|
|
{name: "XORQ/c=-1/dst=BX", inst: XORQ, c: -0x1, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xff}},
|
|
{name: "XORQ/c=11/dst=BX", inst: XORQ, c: 0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xb}},
|
|
{name: "XORQ/c=-11/dst=BX", inst: XORQ, c: -0xb, dstReg: RegBX, exp: []byte{0x48, 0x83, 0xf3, 0xf5}},
|
|
{name: "XORQ/c=1243/dst=BX", inst: XORQ, c: 0x4db, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "XORQ/c=-1234/dst=BX", inst: XORQ, c: -0x4d2, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "XORQ/c=255/dst=BX", inst: XORQ, c: 0xff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0x0, 0x0, 0x0}},
|
|
{name: "XORQ/c=2147483647/dst=BX", inst: XORQ, c: 0x7fffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "XORQ/c=-2147483648/dst=BX", inst: XORQ, c: -0x80000000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "XORQ/c=32767/dst=BX", inst: XORQ, c: 0x7fff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "XORQ/c=4294967295/dst=BX", inst: XORQ, c: 0xffffffff, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0xff, 0xff, 0xff, 0xff}},
|
|
{name: "XORQ/c=-32768/dst=BX", inst: XORQ, c: -0x8000, dstReg: RegBX, exp: []byte{0x48, 0x81, 0xf3, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "XORQ/c=0/dst=R15", inst: XORQ, c: 0x0, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0x0}},
|
|
{name: "XORQ/c=1/dst=R15", inst: XORQ, c: 0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0x1}},
|
|
{name: "XORQ/c=-1/dst=R15", inst: XORQ, c: -0x1, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xff}},
|
|
{name: "XORQ/c=11/dst=R15", inst: XORQ, c: 0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xb}},
|
|
{name: "XORQ/c=-11/dst=R15", inst: XORQ, c: -0xb, dstReg: RegR15, exp: []byte{0x49, 0x83, 0xf7, 0xf5}},
|
|
{name: "XORQ/c=1243/dst=R15", inst: XORQ, c: 0x4db, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "XORQ/c=-1234/dst=R15", inst: XORQ, c: -0x4d2, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "XORQ/c=255/dst=R15", inst: XORQ, c: 0xff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0x0, 0x0, 0x0}},
|
|
{name: "XORQ/c=2147483647/dst=R15", inst: XORQ, c: 0x7fffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "XORQ/c=-2147483648/dst=R15", inst: XORQ, c: -0x80000000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "XORQ/c=32767/dst=R15", inst: XORQ, c: 0x7fff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "XORQ/c=4294967295/dst=R15", inst: XORQ, c: 0xffffffff, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0xff, 0xff, 0xff, 0xff}},
|
|
{name: "XORQ/c=-32768/dst=R15", inst: XORQ, c: -0x8000, dstReg: RegR15, exp: []byte{0x49, 0x81, 0xf7, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "PSLLD/c=0/dst=X3", inst: PSLLD, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x0}},
|
|
{name: "PSLLD/c=1/dst=X3", inst: PSLLD, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x1}},
|
|
{name: "PSLLD/c=-1/dst=X3", inst: PSLLD, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0xff}},
|
|
{name: "PSLLD/c=127/dst=X3", inst: PSLLD, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x7f}},
|
|
{name: "PSLLD/c=-128/dst=X3", inst: PSLLD, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x80}},
|
|
{name: "PSLLD/c=0/dst=X15", inst: PSLLD, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x0}},
|
|
{name: "PSLLD/c=1/dst=X15", inst: PSLLD, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x1}},
|
|
{name: "PSLLD/c=-1/dst=X15", inst: PSLLD, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0xff}},
|
|
{name: "PSLLD/c=127/dst=X15", inst: PSLLD, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x7f}},
|
|
{name: "PSLLD/c=-128/dst=X15", inst: PSLLD, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x80}},
|
|
{name: "PSLLQ/c=0/dst=X3", inst: PSLLQ, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x0}},
|
|
{name: "PSLLQ/c=1/dst=X3", inst: PSLLQ, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x1}},
|
|
{name: "PSLLQ/c=-1/dst=X3", inst: PSLLQ, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0xff}},
|
|
{name: "PSLLQ/c=127/dst=X3", inst: PSLLQ, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x7f}},
|
|
{name: "PSLLQ/c=-128/dst=X3", inst: PSLLQ, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xf3, 0x80}},
|
|
{name: "PSLLQ/c=0/dst=X15", inst: PSLLQ, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x0}},
|
|
{name: "PSLLQ/c=1/dst=X15", inst: PSLLQ, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x1}},
|
|
{name: "PSLLQ/c=-1/dst=X15", inst: PSLLQ, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0xff}},
|
|
{name: "PSLLQ/c=127/dst=X15", inst: PSLLQ, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x7f}},
|
|
{name: "PSLLQ/c=-128/dst=X15", inst: PSLLQ, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xf7, 0x80}},
|
|
{name: "PSLLD/c=0/dst=X3", inst: PSLLD, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x0}},
|
|
{name: "PSLLD/c=1/dst=X3", inst: PSLLD, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x1}},
|
|
{name: "PSLLD/c=-1/dst=X3", inst: PSLLD, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0xff}},
|
|
{name: "PSLLD/c=127/dst=X3", inst: PSLLD, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x7f}},
|
|
{name: "PSLLD/c=-128/dst=X3", inst: PSLLD, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x72, 0xf3, 0x80}},
|
|
{name: "PSLLD/c=0/dst=X15", inst: PSLLD, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x0}},
|
|
{name: "PSLLD/c=1/dst=X15", inst: PSLLD, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x1}},
|
|
{name: "PSLLD/c=-1/dst=X15", inst: PSLLD, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0xff}},
|
|
{name: "PSLLD/c=127/dst=X15", inst: PSLLD, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x7f}},
|
|
{name: "PSLLD/c=-128/dst=X15", inst: PSLLD, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x72, 0xf7, 0x80}},
|
|
{name: "PSRLQ/c=0/dst=X3", inst: PSRLQ, c: 0x0, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x0}},
|
|
{name: "PSRLQ/c=1/dst=X3", inst: PSRLQ, c: 0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x1}},
|
|
{name: "PSRLQ/c=-1/dst=X3", inst: PSRLQ, c: -0x1, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0xff}},
|
|
{name: "PSRLQ/c=127/dst=X3", inst: PSRLQ, c: 0x7f, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x7f}},
|
|
{name: "PSRLQ/c=-128/dst=X3", inst: PSRLQ, c: -0x80, dstReg: RegX3, exp: []byte{0x66, 0xf, 0x73, 0xd3, 0x80}},
|
|
{name: "PSRLQ/c=0/dst=X15", inst: PSRLQ, c: 0x0, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x0}},
|
|
{name: "PSRLQ/c=1/dst=X15", inst: PSRLQ, c: 0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x1}},
|
|
{name: "PSRLQ/c=-1/dst=X15", inst: PSRLQ, c: -0x1, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0xff}},
|
|
{name: "PSRLQ/c=127/dst=X15", inst: PSRLQ, c: 0x7f, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x7f}},
|
|
{name: "PSRLQ/c=-128/dst=X15", inst: PSRLQ, c: -0x80, dstReg: RegX15, exp: []byte{0x66, 0x41, 0xf, 0x73, 0xd7, 0x80}},
|
|
{name: "TESTQ/c=7/dst=R8", inst: TESTQ, c: 0x7, dstReg: RegR8, exp: []byte{0x49, 0xf7, 0xc0, 0x07, 0x00, 0x00, 0x00}},
|
|
{name: "TESTQ/c=17/dst=BX", inst: TESTQ, c: 0x11, dstReg: RegBX, exp: []byte{0x48, 0xf7, 0xc3, 0x11, 0x00, 0x00, 0x00}},
|
|
}
|
|
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
buf := code.NextCodeSection()
|
|
err := a.encodeConstToRegister(buf, &nodeImpl{
|
|
instruction: tc.inst,
|
|
types: operandTypesConstToRegister, srcConst: tc.c, dstReg: tc.dstReg,
|
|
})
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, buf.Bytes(), tc.name)
|
|
}
|
|
}
|
|
|
|
func TestAssemblerImpl_encodeReadInstructionAddress(t *testing.T) {
|
|
t.Run("ok", func(t *testing.T) {
|
|
const targetBeforeInstruction = RET
|
|
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
for _, tc := range []struct {
|
|
name string
|
|
dst asm.Register
|
|
exp []byte
|
|
}{
|
|
{name: "AX", dst: RegAX, exp: []byte{0x48, 0x8d, 0x5, 0x2, 0x0, 0x0, 0x0, 0x99, 0xc3, 0x99}},
|
|
{name: "R8", dst: RegR8, exp: []byte{0x4c, 0x8d, 0x5, 0x2, 0x0, 0x0, 0x0, 0x99, 0xc3, 0x99}},
|
|
} {
|
|
a := NewAssembler()
|
|
|
|
// Setup target.
|
|
a.CompileReadInstructionAddress(tc.dst, targetBeforeInstruction)
|
|
a.CompileStandAlone(CDQ) // Dummy.
|
|
a.CompileStandAlone(targetBeforeInstruction)
|
|
a.CompileStandAlone(CDQ) // Target.
|
|
|
|
buf := code.NextCodeSection()
|
|
err := a.Assemble(buf)
|
|
require.NoError(t, err, tc.name)
|
|
|
|
actual := buf.Bytes()
|
|
require.Equal(t, tc.exp, actual, tc.name)
|
|
}
|
|
})
|
|
t.Run("not found", func(t *testing.T) {
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
a := NewAssembler()
|
|
a.CompileReadInstructionAddress(RegR10, NOP)
|
|
a.CompileStandAlone(CDQ)
|
|
|
|
buf := code.NextCodeSection()
|
|
err := a.Assemble(buf)
|
|
require.EqualError(t, err, "BUG: target instruction not found for read instruction address")
|
|
})
|
|
t.Run("offset too large", func(t *testing.T) {
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
a := NewAssembler()
|
|
a.CompileReadInstructionAddress(RegR10, RET)
|
|
a.CompileStandAlone(RET)
|
|
a.CompileStandAlone(CDQ)
|
|
|
|
buf := code.NextCodeSection()
|
|
|
|
for n := a.root; n != nil; n = n.next {
|
|
n.offsetInBinary = uint64(buf.Len())
|
|
|
|
err := a.encodeNode(buf, n)
|
|
require.NoError(t, err)
|
|
}
|
|
|
|
targetNode := a.current
|
|
targetNode.offsetInBinary = uint64(math.MaxInt64)
|
|
|
|
n := a.readInstructionAddressNodes[0]
|
|
err := a.finalizeReadInstructionAddressNode(nil, n)
|
|
require.EqualError(t, err, "BUG: too large offset for LEAQ instruction")
|
|
})
|
|
}
|
|
|
|
func TestAssemblerImpl_encodeRegisterToConst(t *testing.T) {
|
|
t.Run("error", func(t *testing.T) {
|
|
tests := []struct {
|
|
n *nodeImpl
|
|
expErr string
|
|
}{
|
|
{
|
|
n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToConst, srcReg: RegAX},
|
|
expErr: "ADDL is unsupported for RegisterToConst type",
|
|
},
|
|
}
|
|
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
buf := code.NextCodeSection()
|
|
err := a.encodeRegisterToNone(buf, tc.n)
|
|
require.EqualError(t, err, tc.expErr)
|
|
}
|
|
})
|
|
|
|
tests := []struct {
|
|
name string
|
|
c int64
|
|
inst asm.Instruction
|
|
srcReg asm.Register
|
|
exp []byte
|
|
}{
|
|
{name: "CMPL/src=AX/c=0x0", inst: CMPL, srcReg: RegAX, c: 0x0, exp: []byte{0x83, 0xf8, 0x0}},
|
|
{name: "CMPL/src=AX/c=0x1", inst: CMPL, srcReg: RegAX, c: 0x1, exp: []byte{0x83, 0xf8, 0x1}},
|
|
{name: "CMPL/src=AX/c=-0x1", inst: CMPL, srcReg: RegAX, c: -0x1, exp: []byte{0x83, 0xf8, 0xff}},
|
|
{name: "CMPL/src=AX/c=0x4db", inst: CMPL, srcReg: RegAX, c: 0x4db, exp: []byte{0x3d, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=AX/c=-0x4d2", inst: CMPL, srcReg: RegAX, c: -0x4d2, exp: []byte{0x3d, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=AX/c=0x7fffffff", inst: CMPL, srcReg: RegAX, c: 0x7fffffff, exp: []byte{0x3d, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=AX/c=-0x80000000", inst: CMPL, srcReg: RegAX, c: -0x80000000, exp: []byte{0x3d, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=AX/c=0x7fff", inst: CMPL, srcReg: RegAX, c: 0x7fff, exp: []byte{0x3d, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=AX/c=-0x8000", inst: CMPL, srcReg: RegAX, c: -0x8000, exp: []byte{0x3d, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=BX/c=0x0", inst: CMPL, srcReg: RegBX, c: 0x0, exp: []byte{0x83, 0xfb, 0x0}},
|
|
{name: "CMPL/src=BX/c=0x1", inst: CMPL, srcReg: RegBX, c: 0x1, exp: []byte{0x83, 0xfb, 0x1}},
|
|
{name: "CMPL/src=BX/c=-0x1", inst: CMPL, srcReg: RegBX, c: -0x1, exp: []byte{0x83, 0xfb, 0xff}},
|
|
{name: "CMPL/src=BX/c=0x4db", inst: CMPL, srcReg: RegBX, c: 0x4db, exp: []byte{0x81, 0xfb, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=BX/c=-0x4d2", inst: CMPL, srcReg: RegBX, c: -0x4d2, exp: []byte{0x81, 0xfb, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=BX/c=0x7fffffff", inst: CMPL, srcReg: RegBX, c: 0x7fffffff, exp: []byte{0x81, 0xfb, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=BX/c=-0x80000000", inst: CMPL, srcReg: RegBX, c: -0x80000000, exp: []byte{0x81, 0xfb, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=BX/c=0x7fff", inst: CMPL, srcReg: RegBX, c: 0x7fff, exp: []byte{0x81, 0xfb, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=BX/c=-0x8000", inst: CMPL, srcReg: RegBX, c: -0x8000, exp: []byte{0x81, 0xfb, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=SP/c=0x0", inst: CMPL, srcReg: RegSP, c: 0x0, exp: []byte{0x83, 0xfc, 0x0}},
|
|
{name: "CMPL/src=SP/c=0x1", inst: CMPL, srcReg: RegSP, c: 0x1, exp: []byte{0x83, 0xfc, 0x1}},
|
|
{name: "CMPL/src=SP/c=-0x1", inst: CMPL, srcReg: RegSP, c: -0x1, exp: []byte{0x83, 0xfc, 0xff}},
|
|
{name: "CMPL/src=SP/c=0x4db", inst: CMPL, srcReg: RegSP, c: 0x4db, exp: []byte{0x81, 0xfc, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=SP/c=-0x4d2", inst: CMPL, srcReg: RegSP, c: -0x4d2, exp: []byte{0x81, 0xfc, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=SP/c=0x7fffffff", inst: CMPL, srcReg: RegSP, c: 0x7fffffff, exp: []byte{0x81, 0xfc, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=SP/c=-0x80000000", inst: CMPL, srcReg: RegSP, c: -0x80000000, exp: []byte{0x81, 0xfc, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=SP/c=0x7fff", inst: CMPL, srcReg: RegSP, c: 0x7fff, exp: []byte{0x81, 0xfc, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=SP/c=-0x8000", inst: CMPL, srcReg: RegSP, c: -0x8000, exp: []byte{0x81, 0xfc, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=BP/c=0x0", inst: CMPL, srcReg: RegBP, c: 0x0, exp: []byte{0x83, 0xfd, 0x0}},
|
|
{name: "CMPL/src=BP/c=0x1", inst: CMPL, srcReg: RegBP, c: 0x1, exp: []byte{0x83, 0xfd, 0x1}},
|
|
{name: "CMPL/src=BP/c=-0x1", inst: CMPL, srcReg: RegBP, c: -0x1, exp: []byte{0x83, 0xfd, 0xff}},
|
|
{name: "CMPL/src=BP/c=0x4db", inst: CMPL, srcReg: RegBP, c: 0x4db, exp: []byte{0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=BP/c=-0x4d2", inst: CMPL, srcReg: RegBP, c: -0x4d2, exp: []byte{0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=BP/c=0x7fffffff", inst: CMPL, srcReg: RegBP, c: 0x7fffffff, exp: []byte{0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=BP/c=-0x80000000", inst: CMPL, srcReg: RegBP, c: -0x80000000, exp: []byte{0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=BP/c=0x7fff", inst: CMPL, srcReg: RegBP, c: 0x7fff, exp: []byte{0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=BP/c=-0x8000", inst: CMPL, srcReg: RegBP, c: -0x8000, exp: []byte{0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=SI/c=0x0", inst: CMPL, srcReg: RegSI, c: 0x0, exp: []byte{0x83, 0xfe, 0x0}},
|
|
{name: "CMPL/src=SI/c=0x1", inst: CMPL, srcReg: RegSI, c: 0x1, exp: []byte{0x83, 0xfe, 0x1}},
|
|
{name: "CMPL/src=SI/c=-0x1", inst: CMPL, srcReg: RegSI, c: -0x1, exp: []byte{0x83, 0xfe, 0xff}},
|
|
{name: "CMPL/src=SI/c=0x4db", inst: CMPL, srcReg: RegSI, c: 0x4db, exp: []byte{0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=SI/c=-0x4d2", inst: CMPL, srcReg: RegSI, c: -0x4d2, exp: []byte{0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=SI/c=0x7fffffff", inst: CMPL, srcReg: RegSI, c: 0x7fffffff, exp: []byte{0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=SI/c=-0x80000000", inst: CMPL, srcReg: RegSI, c: -0x80000000, exp: []byte{0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=SI/c=0x7fff", inst: CMPL, srcReg: RegSI, c: 0x7fff, exp: []byte{0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=SI/c=-0x8000", inst: CMPL, srcReg: RegSI, c: -0x8000, exp: []byte{0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=DI/c=0x0", inst: CMPL, srcReg: RegDI, c: 0x0, exp: []byte{0x83, 0xff, 0x0}},
|
|
{name: "CMPL/src=DI/c=0x1", inst: CMPL, srcReg: RegDI, c: 0x1, exp: []byte{0x83, 0xff, 0x1}},
|
|
{name: "CMPL/src=DI/c=-0x1", inst: CMPL, srcReg: RegDI, c: -0x1, exp: []byte{0x83, 0xff, 0xff}},
|
|
{name: "CMPL/src=DI/c=0x4db", inst: CMPL, srcReg: RegDI, c: 0x4db, exp: []byte{0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=DI/c=-0x4d2", inst: CMPL, srcReg: RegDI, c: -0x4d2, exp: []byte{0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=DI/c=0x7fffffff", inst: CMPL, srcReg: RegDI, c: 0x7fffffff, exp: []byte{0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=DI/c=-0x80000000", inst: CMPL, srcReg: RegDI, c: -0x80000000, exp: []byte{0x81, 0xff, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=DI/c=0x7fff", inst: CMPL, srcReg: RegDI, c: 0x7fff, exp: []byte{0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=DI/c=-0x8000", inst: CMPL, srcReg: RegDI, c: -0x8000, exp: []byte{0x81, 0xff, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=R8/c=0x0", inst: CMPL, srcReg: RegR8, c: 0x0, exp: []byte{0x41, 0x83, 0xf8, 0x0}},
|
|
{name: "CMPL/src=R8/c=0x1", inst: CMPL, srcReg: RegR8, c: 0x1, exp: []byte{0x41, 0x83, 0xf8, 0x1}},
|
|
{name: "CMPL/src=R8/c=-0x1", inst: CMPL, srcReg: RegR8, c: -0x1, exp: []byte{0x41, 0x83, 0xf8, 0xff}},
|
|
{name: "CMPL/src=R8/c=0x4db", inst: CMPL, srcReg: RegR8, c: 0x4db, exp: []byte{0x41, 0x81, 0xf8, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=R8/c=-0x4d2", inst: CMPL, srcReg: RegR8, c: -0x4d2, exp: []byte{0x41, 0x81, 0xf8, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=R8/c=0x7fffffff", inst: CMPL, srcReg: RegR8, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xf8, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=R8/c=-0x80000000", inst: CMPL, srcReg: RegR8, c: -0x80000000, exp: []byte{0x41, 0x81, 0xf8, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=R8/c=0x7fff", inst: CMPL, srcReg: RegR8, c: 0x7fff, exp: []byte{0x41, 0x81, 0xf8, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=R8/c=-0x8000", inst: CMPL, srcReg: RegR8, c: -0x8000, exp: []byte{0x41, 0x81, 0xf8, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=R9/c=0x0", inst: CMPL, srcReg: RegR9, c: 0x0, exp: []byte{0x41, 0x83, 0xf9, 0x0}},
|
|
{name: "CMPL/src=R9/c=0x1", inst: CMPL, srcReg: RegR9, c: 0x1, exp: []byte{0x41, 0x83, 0xf9, 0x1}},
|
|
{name: "CMPL/src=R9/c=-0x1", inst: CMPL, srcReg: RegR9, c: -0x1, exp: []byte{0x41, 0x83, 0xf9, 0xff}},
|
|
{name: "CMPL/src=R9/c=0x4db", inst: CMPL, srcReg: RegR9, c: 0x4db, exp: []byte{0x41, 0x81, 0xf9, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=R9/c=-0x4d2", inst: CMPL, srcReg: RegR9, c: -0x4d2, exp: []byte{0x41, 0x81, 0xf9, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=R9/c=0x7fffffff", inst: CMPL, srcReg: RegR9, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xf9, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=R9/c=-0x80000000", inst: CMPL, srcReg: RegR9, c: -0x80000000, exp: []byte{0x41, 0x81, 0xf9, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=R9/c=0x7fff", inst: CMPL, srcReg: RegR9, c: 0x7fff, exp: []byte{0x41, 0x81, 0xf9, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=R9/c=-0x8000", inst: CMPL, srcReg: RegR9, c: -0x8000, exp: []byte{0x41, 0x81, 0xf9, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=R13/c=0x0", inst: CMPL, srcReg: RegR13, c: 0x0, exp: []byte{0x41, 0x83, 0xfd, 0x0}},
|
|
{name: "CMPL/src=R13/c=0x1", inst: CMPL, srcReg: RegR13, c: 0x1, exp: []byte{0x41, 0x83, 0xfd, 0x1}},
|
|
{name: "CMPL/src=R13/c=-0x1", inst: CMPL, srcReg: RegR13, c: -0x1, exp: []byte{0x41, 0x83, 0xfd, 0xff}},
|
|
{name: "CMPL/src=R13/c=0x4db", inst: CMPL, srcReg: RegR13, c: 0x4db, exp: []byte{0x41, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=R13/c=-0x4d2", inst: CMPL, srcReg: RegR13, c: -0x4d2, exp: []byte{0x41, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=R13/c=0x7fffffff", inst: CMPL, srcReg: RegR13, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=R13/c=-0x80000000", inst: CMPL, srcReg: RegR13, c: -0x80000000, exp: []byte{0x41, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=R13/c=0x7fff", inst: CMPL, srcReg: RegR13, c: 0x7fff, exp: []byte{0x41, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=R13/c=-0x8000", inst: CMPL, srcReg: RegR13, c: -0x8000, exp: []byte{0x41, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=R14/c=0x0", inst: CMPL, srcReg: RegR14, c: 0x0, exp: []byte{0x41, 0x83, 0xfe, 0x0}},
|
|
{name: "CMPL/src=R14/c=0x1", inst: CMPL, srcReg: RegR14, c: 0x1, exp: []byte{0x41, 0x83, 0xfe, 0x1}},
|
|
{name: "CMPL/src=R14/c=-0x1", inst: CMPL, srcReg: RegR14, c: -0x1, exp: []byte{0x41, 0x83, 0xfe, 0xff}},
|
|
{name: "CMPL/src=R14/c=0x4db", inst: CMPL, srcReg: RegR14, c: 0x4db, exp: []byte{0x41, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=R14/c=-0x4d2", inst: CMPL, srcReg: RegR14, c: -0x4d2, exp: []byte{0x41, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=R14/c=0x7fffffff", inst: CMPL, srcReg: RegR14, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=R14/c=-0x80000000", inst: CMPL, srcReg: RegR14, c: -0x80000000, exp: []byte{0x41, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=R14/c=0x7fff", inst: CMPL, srcReg: RegR14, c: 0x7fff, exp: []byte{0x41, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=R14/c=-0x8000", inst: CMPL, srcReg: RegR14, c: -0x8000, exp: []byte{0x41, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPL/src=R15/c=0x0", inst: CMPL, srcReg: RegR15, c: 0x0, exp: []byte{0x41, 0x83, 0xff, 0x0}},
|
|
{name: "CMPL/src=R15/c=0x1", inst: CMPL, srcReg: RegR15, c: 0x1, exp: []byte{0x41, 0x83, 0xff, 0x1}},
|
|
{name: "CMPL/src=R15/c=-0x1", inst: CMPL, srcReg: RegR15, c: -0x1, exp: []byte{0x41, 0x83, 0xff, 0xff}},
|
|
{name: "CMPL/src=R15/c=0x4db", inst: CMPL, srcReg: RegR15, c: 0x4db, exp: []byte{0x41, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPL/src=R15/c=-0x4d2", inst: CMPL, srcReg: RegR15, c: -0x4d2, exp: []byte{0x41, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPL/src=R15/c=0x7fffffff", inst: CMPL, srcReg: RegR15, c: 0x7fffffff, exp: []byte{0x41, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPL/src=R15/c=-0x80000000", inst: CMPL, srcReg: RegR15, c: -0x80000000, exp: []byte{0x41, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPL/src=R15/c=0x7fff", inst: CMPL, srcReg: RegR15, c: 0x7fff, exp: []byte{0x41, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPL/src=R15/c=-0x8000", inst: CMPL, srcReg: RegR15, c: -0x8000, exp: []byte{0x41, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=AX/c=0x0", inst: CMPQ, srcReg: RegAX, c: 0x0, exp: []byte{0x48, 0x83, 0xf8, 0x0}},
|
|
{name: "CMPQ/src=AX/c=0x1", inst: CMPQ, srcReg: RegAX, c: 0x1, exp: []byte{0x48, 0x83, 0xf8, 0x1}},
|
|
{name: "CMPQ/src=AX/c=-0x1", inst: CMPQ, srcReg: RegAX, c: -0x1, exp: []byte{0x48, 0x83, 0xf8, 0xff}},
|
|
{name: "CMPQ/src=AX/c=0x4db", inst: CMPQ, srcReg: RegAX, c: 0x4db, exp: []byte{0x48, 0x3d, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=AX/c=-0x4d2", inst: CMPQ, srcReg: RegAX, c: -0x4d2, exp: []byte{0x48, 0x3d, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=AX/c=0x7fffffff", inst: CMPQ, srcReg: RegAX, c: 0x7fffffff, exp: []byte{0x48, 0x3d, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=AX/c=-0x80000000", inst: CMPQ, srcReg: RegAX, c: -0x80000000, exp: []byte{0x48, 0x3d, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=AX/c=0x7fff", inst: CMPQ, srcReg: RegAX, c: 0x7fff, exp: []byte{0x48, 0x3d, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=AX/c=-0x8000", inst: CMPQ, srcReg: RegAX, c: -0x8000, exp: []byte{0x48, 0x3d, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=BX/c=0x0", inst: CMPQ, srcReg: RegBX, c: 0x0, exp: []byte{0x48, 0x83, 0xfb, 0x0}},
|
|
{name: "CMPQ/src=BX/c=0x1", inst: CMPQ, srcReg: RegBX, c: 0x1, exp: []byte{0x48, 0x83, 0xfb, 0x1}},
|
|
{name: "CMPQ/src=BX/c=-0x1", inst: CMPQ, srcReg: RegBX, c: -0x1, exp: []byte{0x48, 0x83, 0xfb, 0xff}},
|
|
{name: "CMPQ/src=BX/c=0x4db", inst: CMPQ, srcReg: RegBX, c: 0x4db, exp: []byte{0x48, 0x81, 0xfb, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=BX/c=-0x4d2", inst: CMPQ, srcReg: RegBX, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfb, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=BX/c=0x7fffffff", inst: CMPQ, srcReg: RegBX, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfb, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=BX/c=-0x80000000", inst: CMPQ, srcReg: RegBX, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfb, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=BX/c=0x7fff", inst: CMPQ, srcReg: RegBX, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfb, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=BX/c=-0x8000", inst: CMPQ, srcReg: RegBX, c: -0x8000, exp: []byte{0x48, 0x81, 0xfb, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=SP/c=0x0", inst: CMPQ, srcReg: RegSP, c: 0x0, exp: []byte{0x48, 0x83, 0xfc, 0x0}},
|
|
{name: "CMPQ/src=SP/c=0x1", inst: CMPQ, srcReg: RegSP, c: 0x1, exp: []byte{0x48, 0x83, 0xfc, 0x1}},
|
|
{name: "CMPQ/src=SP/c=-0x1", inst: CMPQ, srcReg: RegSP, c: -0x1, exp: []byte{0x48, 0x83, 0xfc, 0xff}},
|
|
{name: "CMPQ/src=SP/c=0x4db", inst: CMPQ, srcReg: RegSP, c: 0x4db, exp: []byte{0x48, 0x81, 0xfc, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=SP/c=-0x4d2", inst: CMPQ, srcReg: RegSP, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfc, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=SP/c=0x7fffffff", inst: CMPQ, srcReg: RegSP, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfc, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=SP/c=-0x80000000", inst: CMPQ, srcReg: RegSP, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfc, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=SP/c=0x7fff", inst: CMPQ, srcReg: RegSP, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfc, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=SP/c=-0x8000", inst: CMPQ, srcReg: RegSP, c: -0x8000, exp: []byte{0x48, 0x81, 0xfc, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=BP/c=0x0", inst: CMPQ, srcReg: RegBP, c: 0x0, exp: []byte{0x48, 0x83, 0xfd, 0x0}},
|
|
{name: "CMPQ/src=BP/c=0x1", inst: CMPQ, srcReg: RegBP, c: 0x1, exp: []byte{0x48, 0x83, 0xfd, 0x1}},
|
|
{name: "CMPQ/src=BP/c=-0x1", inst: CMPQ, srcReg: RegBP, c: -0x1, exp: []byte{0x48, 0x83, 0xfd, 0xff}},
|
|
{name: "CMPQ/src=BP/c=0x4db", inst: CMPQ, srcReg: RegBP, c: 0x4db, exp: []byte{0x48, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=BP/c=-0x4d2", inst: CMPQ, srcReg: RegBP, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=BP/c=0x7fffffff", inst: CMPQ, srcReg: RegBP, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=BP/c=-0x80000000", inst: CMPQ, srcReg: RegBP, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=BP/c=0x7fff", inst: CMPQ, srcReg: RegBP, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=BP/c=-0x8000", inst: CMPQ, srcReg: RegBP, c: -0x8000, exp: []byte{0x48, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=SI/c=0x0", inst: CMPQ, srcReg: RegSI, c: 0x0, exp: []byte{0x48, 0x83, 0xfe, 0x0}},
|
|
{name: "CMPQ/src=SI/c=0x1", inst: CMPQ, srcReg: RegSI, c: 0x1, exp: []byte{0x48, 0x83, 0xfe, 0x1}},
|
|
{name: "CMPQ/src=SI/c=-0x1", inst: CMPQ, srcReg: RegSI, c: -0x1, exp: []byte{0x48, 0x83, 0xfe, 0xff}},
|
|
{name: "CMPQ/src=SI/c=0x4db", inst: CMPQ, srcReg: RegSI, c: 0x4db, exp: []byte{0x48, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=SI/c=-0x4d2", inst: CMPQ, srcReg: RegSI, c: -0x4d2, exp: []byte{0x48, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=SI/c=0x7fffffff", inst: CMPQ, srcReg: RegSI, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=SI/c=-0x80000000", inst: CMPQ, srcReg: RegSI, c: -0x80000000, exp: []byte{0x48, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=SI/c=0x7fff", inst: CMPQ, srcReg: RegSI, c: 0x7fff, exp: []byte{0x48, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=SI/c=-0x8000", inst: CMPQ, srcReg: RegSI, c: -0x8000, exp: []byte{0x48, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=DI/c=0x0", inst: CMPQ, srcReg: RegDI, c: 0x0, exp: []byte{0x48, 0x83, 0xff, 0x0}},
|
|
{name: "CMPQ/src=DI/c=0x1", inst: CMPQ, srcReg: RegDI, c: 0x1, exp: []byte{0x48, 0x83, 0xff, 0x1}},
|
|
{name: "CMPQ/src=DI/c=-0x1", inst: CMPQ, srcReg: RegDI, c: -0x1, exp: []byte{0x48, 0x83, 0xff, 0xff}},
|
|
{name: "CMPQ/src=DI/c=0x4db", inst: CMPQ, srcReg: RegDI, c: 0x4db, exp: []byte{0x48, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=DI/c=-0x4d2", inst: CMPQ, srcReg: RegDI, c: -0x4d2, exp: []byte{0x48, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=DI/c=0x7fffffff", inst: CMPQ, srcReg: RegDI, c: 0x7fffffff, exp: []byte{0x48, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=DI/c=-0x80000000", inst: CMPQ, srcReg: RegDI, c: -0x80000000, exp: []byte{0x48, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=DI/c=0x7fff", inst: CMPQ, srcReg: RegDI, c: 0x7fff, exp: []byte{0x48, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=DI/c=-0x8000", inst: CMPQ, srcReg: RegDI, c: -0x8000, exp: []byte{0x48, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R8/c=0x0", inst: CMPQ, srcReg: RegR8, c: 0x0, exp: []byte{0x49, 0x83, 0xf8, 0x0}},
|
|
{name: "CMPQ/src=R8/c=0x1", inst: CMPQ, srcReg: RegR8, c: 0x1, exp: []byte{0x49, 0x83, 0xf8, 0x1}},
|
|
{name: "CMPQ/src=R8/c=-0x1", inst: CMPQ, srcReg: RegR8, c: -0x1, exp: []byte{0x49, 0x83, 0xf8, 0xff}},
|
|
{name: "CMPQ/src=R8/c=0x4db", inst: CMPQ, srcReg: RegR8, c: 0x4db, exp: []byte{0x49, 0x81, 0xf8, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R8/c=-0x4d2", inst: CMPQ, srcReg: RegR8, c: -0x4d2, exp: []byte{0x49, 0x81, 0xf8, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R8/c=0x7fffffff", inst: CMPQ, srcReg: RegR8, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xf8, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=R8/c=-0x80000000", inst: CMPQ, srcReg: RegR8, c: -0x80000000, exp: []byte{0x49, 0x81, 0xf8, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=R8/c=0x7fff", inst: CMPQ, srcReg: RegR8, c: 0x7fff, exp: []byte{0x49, 0x81, 0xf8, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R8/c=-0x8000", inst: CMPQ, srcReg: RegR8, c: -0x8000, exp: []byte{0x49, 0x81, 0xf8, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R9/c=0x0", inst: CMPQ, srcReg: RegR9, c: 0x0, exp: []byte{0x49, 0x83, 0xf9, 0x0}},
|
|
{name: "CMPQ/src=R9/c=0x1", inst: CMPQ, srcReg: RegR9, c: 0x1, exp: []byte{0x49, 0x83, 0xf9, 0x1}},
|
|
{name: "CMPQ/src=R9/c=-0x1", inst: CMPQ, srcReg: RegR9, c: -0x1, exp: []byte{0x49, 0x83, 0xf9, 0xff}},
|
|
{name: "CMPQ/src=R9/c=0x4db", inst: CMPQ, srcReg: RegR9, c: 0x4db, exp: []byte{0x49, 0x81, 0xf9, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R9/c=-0x4d2", inst: CMPQ, srcReg: RegR9, c: -0x4d2, exp: []byte{0x49, 0x81, 0xf9, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R9/c=0x7fffffff", inst: CMPQ, srcReg: RegR9, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xf9, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=R9/c=-0x80000000", inst: CMPQ, srcReg: RegR9, c: -0x80000000, exp: []byte{0x49, 0x81, 0xf9, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=R9/c=0x7fff", inst: CMPQ, srcReg: RegR9, c: 0x7fff, exp: []byte{0x49, 0x81, 0xf9, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R9/c=-0x8000", inst: CMPQ, srcReg: RegR9, c: -0x8000, exp: []byte{0x49, 0x81, 0xf9, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R13/c=0x0", inst: CMPQ, srcReg: RegR13, c: 0x0, exp: []byte{0x49, 0x83, 0xfd, 0x0}},
|
|
{name: "CMPQ/src=R13/c=0x1", inst: CMPQ, srcReg: RegR13, c: 0x1, exp: []byte{0x49, 0x83, 0xfd, 0x1}},
|
|
{name: "CMPQ/src=R13/c=-0x1", inst: CMPQ, srcReg: RegR13, c: -0x1, exp: []byte{0x49, 0x83, 0xfd, 0xff}},
|
|
{name: "CMPQ/src=R13/c=0x4db", inst: CMPQ, srcReg: RegR13, c: 0x4db, exp: []byte{0x49, 0x81, 0xfd, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R13/c=-0x4d2", inst: CMPQ, srcReg: RegR13, c: -0x4d2, exp: []byte{0x49, 0x81, 0xfd, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R13/c=0x7fffffff", inst: CMPQ, srcReg: RegR13, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xfd, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=R13/c=-0x80000000", inst: CMPQ, srcReg: RegR13, c: -0x80000000, exp: []byte{0x49, 0x81, 0xfd, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=R13/c=0x7fff", inst: CMPQ, srcReg: RegR13, c: 0x7fff, exp: []byte{0x49, 0x81, 0xfd, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R13/c=-0x8000", inst: CMPQ, srcReg: RegR13, c: -0x8000, exp: []byte{0x49, 0x81, 0xfd, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R14/c=0x0", inst: CMPQ, srcReg: RegR14, c: 0x0, exp: []byte{0x49, 0x83, 0xfe, 0x0}},
|
|
{name: "CMPQ/src=R14/c=0x1", inst: CMPQ, srcReg: RegR14, c: 0x1, exp: []byte{0x49, 0x83, 0xfe, 0x1}},
|
|
{name: "CMPQ/src=R14/c=-0x1", inst: CMPQ, srcReg: RegR14, c: -0x1, exp: []byte{0x49, 0x83, 0xfe, 0xff}},
|
|
{name: "CMPQ/src=R14/c=0x4db", inst: CMPQ, srcReg: RegR14, c: 0x4db, exp: []byte{0x49, 0x81, 0xfe, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R14/c=-0x4d2", inst: CMPQ, srcReg: RegR14, c: -0x4d2, exp: []byte{0x49, 0x81, 0xfe, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R14/c=0x7fffffff", inst: CMPQ, srcReg: RegR14, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xfe, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=R14/c=-0x80000000", inst: CMPQ, srcReg: RegR14, c: -0x80000000, exp: []byte{0x49, 0x81, 0xfe, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=R14/c=0x7fff", inst: CMPQ, srcReg: RegR14, c: 0x7fff, exp: []byte{0x49, 0x81, 0xfe, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R14/c=-0x8000", inst: CMPQ, srcReg: RegR14, c: -0x8000, exp: []byte{0x49, 0x81, 0xfe, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R15/c=0x0", inst: CMPQ, srcReg: RegR15, c: 0x0, exp: []byte{0x49, 0x83, 0xff, 0x0}},
|
|
{name: "CMPQ/src=R15/c=0x1", inst: CMPQ, srcReg: RegR15, c: 0x1, exp: []byte{0x49, 0x83, 0xff, 0x1}},
|
|
{name: "CMPQ/src=R15/c=-0x1", inst: CMPQ, srcReg: RegR15, c: -0x1, exp: []byte{0x49, 0x83, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R15/c=0x4db", inst: CMPQ, srcReg: RegR15, c: 0x4db, exp: []byte{0x49, 0x81, 0xff, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R15/c=-0x4d2", inst: CMPQ, srcReg: RegR15, c: -0x4d2, exp: []byte{0x49, 0x81, 0xff, 0x2e, 0xfb, 0xff, 0xff}},
|
|
{name: "CMPQ/src=R15/c=0x7fffffff", inst: CMPQ, srcReg: RegR15, c: 0x7fffffff, exp: []byte{0x49, 0x81, 0xff, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "CMPQ/src=R15/c=-0x80000000", inst: CMPQ, srcReg: RegR15, c: -0x80000000, exp: []byte{0x49, 0x81, 0xff, 0x0, 0x0, 0x0, 0x80}},
|
|
{name: "CMPQ/src=R15/c=0x7fff", inst: CMPQ, srcReg: RegR15, c: 0x7fff, exp: []byte{0x49, 0x81, 0xff, 0xff, 0x7f, 0x0, 0x0}},
|
|
{name: "CMPQ/src=R15/c=-0x8000", inst: CMPQ, srcReg: RegR15, c: -0x8000, exp: []byte{0x49, 0x81, 0xff, 0x0, 0x80, 0xff, 0xff}},
|
|
}
|
|
|
|
code := asm.CodeSegment{}
|
|
defer func() { require.NoError(t, code.Unmap()) }()
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
buf := code.NextCodeSection()
|
|
err := a.encodeRegisterToConst(buf, &nodeImpl{
|
|
instruction: tc.inst,
|
|
types: operandTypesRegisterToConst, srcReg: tc.srcReg, dstConst: tc.c,
|
|
})
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, buf.Bytes(), tc.name)
|
|
}
|
|
}
|
|
|
|
func TestNodeImpl_GetRegisterToRegisterModRM(t *testing.T) {
|
|
tests := []struct {
|
|
name string
|
|
srcReg, dstReg asm.Register
|
|
srcOnModRMReg bool
|
|
expRexPrefix, expModRM byte
|
|
}{
|
|
{name: "src=AX/dst=AX/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc0},
|
|
{name: "src=AX/dst=BX/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc3},
|
|
{name: "src=AX/dst=SP/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc4},
|
|
{name: "src=AX/dst=BP/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc5},
|
|
{name: "src=AX/dst=SI/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc6},
|
|
{name: "src=AX/dst=DI/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xc7},
|
|
{name: "src=AX/dst=R8/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc0},
|
|
{name: "src=AX/dst=R9/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc1},
|
|
{name: "src=AX/dst=R13/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc5},
|
|
{name: "src=AX/dst=R14/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc6},
|
|
{name: "src=AX/dst=R15/srcOnModRMReg=true", srcReg: RegAX, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xc7},
|
|
{name: "src=BX/dst=AX/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xd8},
|
|
{name: "src=BX/dst=BX/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdb},
|
|
{name: "src=BX/dst=SP/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdc},
|
|
{name: "src=BX/dst=BP/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdd},
|
|
{name: "src=BX/dst=SI/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xde},
|
|
{name: "src=BX/dst=DI/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xdf},
|
|
{name: "src=BX/dst=R8/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xd8},
|
|
{name: "src=BX/dst=R9/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xd9},
|
|
{name: "src=BX/dst=R13/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xdd},
|
|
{name: "src=BX/dst=R14/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xde},
|
|
{name: "src=BX/dst=R15/srcOnModRMReg=true", srcReg: RegBX, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xdf},
|
|
{name: "src=SP/dst=AX/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe0},
|
|
{name: "src=SP/dst=BX/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe3},
|
|
{name: "src=SP/dst=SP/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe4},
|
|
{name: "src=SP/dst=BP/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe5},
|
|
{name: "src=SP/dst=SI/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe6},
|
|
{name: "src=SP/dst=DI/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe7},
|
|
{name: "src=SP/dst=R8/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe0},
|
|
{name: "src=SP/dst=R9/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe1},
|
|
{name: "src=SP/dst=R13/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe5},
|
|
{name: "src=SP/dst=R14/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe6},
|
|
{name: "src=SP/dst=R15/srcOnModRMReg=true", srcReg: RegSP, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe7},
|
|
{name: "src=BP/dst=AX/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xe8},
|
|
{name: "src=BP/dst=BX/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xeb},
|
|
{name: "src=BP/dst=SP/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xec},
|
|
{name: "src=BP/dst=BP/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xed},
|
|
{name: "src=BP/dst=SI/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xee},
|
|
{name: "src=BP/dst=DI/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xef},
|
|
{name: "src=BP/dst=R8/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe8},
|
|
{name: "src=BP/dst=R9/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xe9},
|
|
{name: "src=BP/dst=R13/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xed},
|
|
{name: "src=BP/dst=R14/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xee},
|
|
{name: "src=BP/dst=R15/srcOnModRMReg=true", srcReg: RegBP, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xef},
|
|
{name: "src=SI/dst=AX/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf0},
|
|
{name: "src=SI/dst=BX/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf3},
|
|
{name: "src=SI/dst=SP/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf4},
|
|
{name: "src=SI/dst=BP/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf5},
|
|
{name: "src=SI/dst=SI/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf6},
|
|
{name: "src=SI/dst=DI/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf7},
|
|
{name: "src=SI/dst=R8/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf0},
|
|
{name: "src=SI/dst=R9/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf1},
|
|
{name: "src=SI/dst=R13/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf5},
|
|
{name: "src=SI/dst=R14/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf6},
|
|
{name: "src=SI/dst=R15/srcOnModRMReg=true", srcReg: RegSI, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf7},
|
|
{name: "src=DI/dst=AX/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xf8},
|
|
{name: "src=DI/dst=BX/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfb},
|
|
{name: "src=DI/dst=SP/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfc},
|
|
{name: "src=DI/dst=BP/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfd},
|
|
{name: "src=DI/dst=SI/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xfe},
|
|
{name: "src=DI/dst=DI/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x0, expModRM: 0xff},
|
|
{name: "src=DI/dst=R8/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf8},
|
|
{name: "src=DI/dst=R9/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xf9},
|
|
{name: "src=DI/dst=R13/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xfd},
|
|
{name: "src=DI/dst=R14/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xfe},
|
|
{name: "src=DI/dst=R15/srcOnModRMReg=true", srcReg: RegDI, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x41, expModRM: 0xff},
|
|
{name: "src=R8/dst=AX/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc0},
|
|
{name: "src=R8/dst=BX/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc3},
|
|
{name: "src=R8/dst=SP/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc4},
|
|
{name: "src=R8/dst=BP/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc5},
|
|
{name: "src=R8/dst=SI/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc6},
|
|
{name: "src=R8/dst=DI/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc7},
|
|
{name: "src=R8/dst=R8/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc0},
|
|
{name: "src=R8/dst=R9/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc1},
|
|
{name: "src=R8/dst=R13/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc5},
|
|
{name: "src=R8/dst=R14/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc6},
|
|
{name: "src=R8/dst=R15/srcOnModRMReg=true", srcReg: RegR8, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc7},
|
|
{name: "src=R9/dst=AX/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xc8},
|
|
{name: "src=R9/dst=BX/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcb},
|
|
{name: "src=R9/dst=SP/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcc},
|
|
{name: "src=R9/dst=BP/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcd},
|
|
{name: "src=R9/dst=SI/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xce},
|
|
{name: "src=R9/dst=DI/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xcf},
|
|
{name: "src=R9/dst=R8/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc8},
|
|
{name: "src=R9/dst=R9/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xc9},
|
|
{name: "src=R9/dst=R13/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xcd},
|
|
{name: "src=R9/dst=R14/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xce},
|
|
{name: "src=R9/dst=R15/srcOnModRMReg=true", srcReg: RegR9, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xcf},
|
|
{name: "src=R13/dst=AX/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xe8},
|
|
{name: "src=R13/dst=BX/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xeb},
|
|
{name: "src=R13/dst=SP/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xec},
|
|
{name: "src=R13/dst=BP/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xed},
|
|
{name: "src=R13/dst=SI/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xee},
|
|
{name: "src=R13/dst=DI/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xef},
|
|
{name: "src=R13/dst=R8/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xe8},
|
|
{name: "src=R13/dst=R9/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xe9},
|
|
{name: "src=R13/dst=R13/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xed},
|
|
{name: "src=R13/dst=R14/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xee},
|
|
{name: "src=R13/dst=R15/srcOnModRMReg=true", srcReg: RegR13, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xef},
|
|
{name: "src=R14/dst=AX/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf0},
|
|
{name: "src=R14/dst=BX/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf3},
|
|
{name: "src=R14/dst=SP/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf4},
|
|
{name: "src=R14/dst=BP/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf5},
|
|
{name: "src=R14/dst=SI/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf6},
|
|
{name: "src=R14/dst=DI/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf7},
|
|
{name: "src=R14/dst=R8/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf0},
|
|
{name: "src=R14/dst=R9/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf1},
|
|
{name: "src=R14/dst=R13/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf5},
|
|
{name: "src=R14/dst=R14/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf6},
|
|
{name: "src=R14/dst=R15/srcOnModRMReg=true", srcReg: RegR14, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf7},
|
|
{name: "src=R15/dst=AX/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegAX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xf8},
|
|
{name: "src=R15/dst=BX/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegBX, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfb},
|
|
{name: "src=R15/dst=SP/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegSP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfc},
|
|
{name: "src=R15/dst=BP/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegBP, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfd},
|
|
{name: "src=R15/dst=SI/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegSI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xfe},
|
|
{name: "src=R15/dst=DI/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegDI, srcOnModRMReg: true, expRexPrefix: 0x44, expModRM: 0xff},
|
|
{name: "src=R15/dst=R8/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR8, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf8},
|
|
{name: "src=R15/dst=R9/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR9, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xf9},
|
|
{name: "src=R15/dst=R13/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR13, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xfd},
|
|
{name: "src=R15/dst=R14/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR14, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xfe},
|
|
{name: "src=R15/dst=R15/srcOnModRMReg=true", srcReg: RegR15, dstReg: RegR15, srcOnModRMReg: true, expRexPrefix: 0x45, expModRM: 0xff},
|
|
{name: "src=AX/dst=AX/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0},
|
|
{name: "src=AX/dst=BX/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8},
|
|
{name: "src=AX/dst=SP/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0},
|
|
{name: "src=AX/dst=BP/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8},
|
|
{name: "src=AX/dst=SI/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0},
|
|
{name: "src=AX/dst=DI/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8},
|
|
{name: "src=AX/dst=R8/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0},
|
|
{name: "src=AX/dst=R9/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8},
|
|
{name: "src=AX/dst=R13/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8},
|
|
{name: "src=AX/dst=R14/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0},
|
|
{name: "src=AX/dst=R15/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8},
|
|
{name: "src=BX/dst=AX/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3},
|
|
{name: "src=BX/dst=BX/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb},
|
|
{name: "src=BX/dst=SP/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3},
|
|
{name: "src=BX/dst=BP/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb},
|
|
{name: "src=BX/dst=SI/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3},
|
|
{name: "src=BX/dst=DI/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb},
|
|
{name: "src=BX/dst=R8/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3},
|
|
{name: "src=BX/dst=R9/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb},
|
|
{name: "src=BX/dst=R13/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb},
|
|
{name: "src=BX/dst=R14/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3},
|
|
{name: "src=BX/dst=R15/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb},
|
|
{name: "src=SP/dst=AX/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4},
|
|
{name: "src=SP/dst=BX/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc},
|
|
{name: "src=SP/dst=SP/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4},
|
|
{name: "src=SP/dst=BP/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec},
|
|
{name: "src=SP/dst=SI/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4},
|
|
{name: "src=SP/dst=DI/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc},
|
|
{name: "src=SP/dst=R8/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4},
|
|
{name: "src=SP/dst=R9/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc},
|
|
{name: "src=SP/dst=R13/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec},
|
|
{name: "src=SP/dst=R14/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4},
|
|
{name: "src=SP/dst=R15/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc},
|
|
{name: "src=BP/dst=AX/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5},
|
|
{name: "src=BP/dst=BX/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd},
|
|
{name: "src=BP/dst=SP/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5},
|
|
{name: "src=BP/dst=BP/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed},
|
|
{name: "src=BP/dst=SI/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5},
|
|
{name: "src=BP/dst=DI/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd},
|
|
{name: "src=BP/dst=R8/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5},
|
|
{name: "src=BP/dst=R9/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd},
|
|
{name: "src=BP/dst=R13/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed},
|
|
{name: "src=BP/dst=R14/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5},
|
|
{name: "src=BP/dst=R15/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd},
|
|
{name: "src=SI/dst=AX/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6},
|
|
{name: "src=SI/dst=BX/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde},
|
|
{name: "src=SI/dst=SP/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6},
|
|
{name: "src=SI/dst=BP/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee},
|
|
{name: "src=SI/dst=SI/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6},
|
|
{name: "src=SI/dst=DI/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe},
|
|
{name: "src=SI/dst=R8/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6},
|
|
{name: "src=SI/dst=R9/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce},
|
|
{name: "src=SI/dst=R13/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee},
|
|
{name: "src=SI/dst=R14/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6},
|
|
{name: "src=SI/dst=R15/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe},
|
|
{name: "src=DI/dst=AX/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7},
|
|
{name: "src=DI/dst=BX/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf},
|
|
{name: "src=DI/dst=SP/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7},
|
|
{name: "src=DI/dst=BP/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef},
|
|
{name: "src=DI/dst=SI/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7},
|
|
{name: "src=DI/dst=DI/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff},
|
|
{name: "src=DI/dst=R8/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7},
|
|
{name: "src=DI/dst=R9/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf},
|
|
{name: "src=DI/dst=R13/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef},
|
|
{name: "src=DI/dst=R14/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7},
|
|
{name: "src=DI/dst=R15/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff},
|
|
{name: "src=R8/dst=AX/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0},
|
|
{name: "src=R8/dst=BX/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8},
|
|
{name: "src=R8/dst=SP/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0},
|
|
{name: "src=R8/dst=BP/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8},
|
|
{name: "src=R8/dst=SI/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0},
|
|
{name: "src=R8/dst=DI/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8},
|
|
{name: "src=R8/dst=R8/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0},
|
|
{name: "src=R8/dst=R9/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8},
|
|
{name: "src=R8/dst=R13/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8},
|
|
{name: "src=R8/dst=R14/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0},
|
|
{name: "src=R8/dst=R15/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8},
|
|
{name: "src=R9/dst=AX/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1},
|
|
{name: "src=R9/dst=BX/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9},
|
|
{name: "src=R9/dst=SP/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1},
|
|
{name: "src=R9/dst=BP/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9},
|
|
{name: "src=R9/dst=SI/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1},
|
|
{name: "src=R9/dst=DI/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9},
|
|
{name: "src=R9/dst=R8/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1},
|
|
{name: "src=R9/dst=R9/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9},
|
|
{name: "src=R9/dst=R13/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9},
|
|
{name: "src=R9/dst=R14/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1},
|
|
{name: "src=R9/dst=R15/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9},
|
|
{name: "src=R13/dst=AX/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5},
|
|
{name: "src=R13/dst=BX/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd},
|
|
{name: "src=R13/dst=SP/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5},
|
|
{name: "src=R13/dst=BP/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed},
|
|
{name: "src=R13/dst=SI/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5},
|
|
{name: "src=R13/dst=DI/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd},
|
|
{name: "src=R13/dst=R8/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5},
|
|
{name: "src=R13/dst=R9/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd},
|
|
{name: "src=R13/dst=R13/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed},
|
|
{name: "src=R13/dst=R14/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5},
|
|
{name: "src=R13/dst=R15/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd},
|
|
{name: "src=R14/dst=AX/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6},
|
|
{name: "src=R14/dst=BX/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde},
|
|
{name: "src=R14/dst=SP/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6},
|
|
{name: "src=R14/dst=BP/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee},
|
|
{name: "src=R14/dst=SI/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6},
|
|
{name: "src=R14/dst=DI/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe},
|
|
{name: "src=R14/dst=R8/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6},
|
|
{name: "src=R14/dst=R9/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce},
|
|
{name: "src=R14/dst=R13/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee},
|
|
{name: "src=R14/dst=R14/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6},
|
|
{name: "src=R14/dst=R15/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe},
|
|
{name: "src=R15/dst=AX/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7},
|
|
{name: "src=R15/dst=BX/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf},
|
|
{name: "src=R15/dst=SP/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7},
|
|
{name: "src=R15/dst=BP/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef},
|
|
{name: "src=R15/dst=SI/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7},
|
|
{name: "src=R15/dst=DI/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff},
|
|
{name: "src=R15/dst=R8/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7},
|
|
{name: "src=R15/dst=R9/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf},
|
|
{name: "src=R15/dst=R13/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef},
|
|
{name: "src=R15/dst=R14/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7},
|
|
{name: "src=R15/dst=R15/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff},
|
|
{name: "src=X0/dst=X0/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0},
|
|
{name: "src=X0/dst=X1/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc8},
|
|
{name: "src=X0/dst=X2/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd0},
|
|
{name: "src=X0/dst=X3/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8},
|
|
{name: "src=X0/dst=X4/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0},
|
|
{name: "src=X0/dst=X5/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8},
|
|
{name: "src=X0/dst=X6/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0},
|
|
{name: "src=X0/dst=X7/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8},
|
|
{name: "src=X0/dst=X8/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0},
|
|
{name: "src=X0/dst=X9/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8},
|
|
{name: "src=X0/dst=X10/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd0},
|
|
{name: "src=X0/dst=X11/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd8},
|
|
{name: "src=X0/dst=X12/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe0},
|
|
{name: "src=X0/dst=X13/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8},
|
|
{name: "src=X0/dst=X14/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0},
|
|
{name: "src=X0/dst=X15/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8},
|
|
{name: "src=X1/dst=X0/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc1},
|
|
{name: "src=X1/dst=X1/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc9},
|
|
{name: "src=X1/dst=X2/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd1},
|
|
{name: "src=X1/dst=X3/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd9},
|
|
{name: "src=X1/dst=X4/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe1},
|
|
{name: "src=X1/dst=X5/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe9},
|
|
{name: "src=X1/dst=X6/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf1},
|
|
{name: "src=X1/dst=X7/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf9},
|
|
{name: "src=X1/dst=X8/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc1},
|
|
{name: "src=X1/dst=X9/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc9},
|
|
{name: "src=X1/dst=X10/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd1},
|
|
{name: "src=X1/dst=X11/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd9},
|
|
{name: "src=X1/dst=X12/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe1},
|
|
{name: "src=X1/dst=X13/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe9},
|
|
{name: "src=X1/dst=X14/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf1},
|
|
{name: "src=X1/dst=X15/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf9},
|
|
{name: "src=X2/dst=X0/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc2},
|
|
{name: "src=X2/dst=X1/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xca},
|
|
{name: "src=X2/dst=X2/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd2},
|
|
{name: "src=X2/dst=X3/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xda},
|
|
{name: "src=X2/dst=X4/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe2},
|
|
{name: "src=X2/dst=X5/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xea},
|
|
{name: "src=X2/dst=X6/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf2},
|
|
{name: "src=X2/dst=X7/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfa},
|
|
{name: "src=X2/dst=X8/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc2},
|
|
{name: "src=X2/dst=X9/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xca},
|
|
{name: "src=X2/dst=X10/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd2},
|
|
{name: "src=X2/dst=X11/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xda},
|
|
{name: "src=X2/dst=X12/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe2},
|
|
{name: "src=X2/dst=X13/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xea},
|
|
{name: "src=X2/dst=X14/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf2},
|
|
{name: "src=X2/dst=X15/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfa},
|
|
{name: "src=X3/dst=X0/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3},
|
|
{name: "src=X3/dst=X1/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcb},
|
|
{name: "src=X3/dst=X2/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd3},
|
|
{name: "src=X3/dst=X3/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb},
|
|
{name: "src=X3/dst=X4/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3},
|
|
{name: "src=X3/dst=X5/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb},
|
|
{name: "src=X3/dst=X6/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3},
|
|
{name: "src=X3/dst=X7/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb},
|
|
{name: "src=X3/dst=X8/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3},
|
|
{name: "src=X3/dst=X9/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb},
|
|
{name: "src=X3/dst=X10/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd3},
|
|
{name: "src=X3/dst=X11/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdb},
|
|
{name: "src=X3/dst=X12/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe3},
|
|
{name: "src=X3/dst=X13/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb},
|
|
{name: "src=X3/dst=X14/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3},
|
|
{name: "src=X3/dst=X15/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb},
|
|
{name: "src=X4/dst=X0/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4},
|
|
{name: "src=X4/dst=X1/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcc},
|
|
{name: "src=X4/dst=X2/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd4},
|
|
{name: "src=X4/dst=X3/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc},
|
|
{name: "src=X4/dst=X4/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4},
|
|
{name: "src=X4/dst=X5/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec},
|
|
{name: "src=X4/dst=X6/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4},
|
|
{name: "src=X4/dst=X7/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc},
|
|
{name: "src=X4/dst=X8/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4},
|
|
{name: "src=X4/dst=X9/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc},
|
|
{name: "src=X4/dst=X10/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd4},
|
|
{name: "src=X4/dst=X11/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdc},
|
|
{name: "src=X4/dst=X12/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe4},
|
|
{name: "src=X4/dst=X13/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec},
|
|
{name: "src=X4/dst=X14/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4},
|
|
{name: "src=X4/dst=X15/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc},
|
|
{name: "src=X5/dst=X0/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5},
|
|
{name: "src=X5/dst=X1/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcd},
|
|
{name: "src=X5/dst=X2/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd5},
|
|
{name: "src=X5/dst=X3/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd},
|
|
{name: "src=X5/dst=X4/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5},
|
|
{name: "src=X5/dst=X5/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed},
|
|
{name: "src=X5/dst=X6/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5},
|
|
{name: "src=X5/dst=X7/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd},
|
|
{name: "src=X5/dst=X8/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5},
|
|
{name: "src=X5/dst=X9/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd},
|
|
{name: "src=X5/dst=X10/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd5},
|
|
{name: "src=X5/dst=X11/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdd},
|
|
{name: "src=X5/dst=X12/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe5},
|
|
{name: "src=X5/dst=X13/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed},
|
|
{name: "src=X5/dst=X14/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5},
|
|
{name: "src=X5/dst=X15/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd},
|
|
{name: "src=X6/dst=X0/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6},
|
|
{name: "src=X6/dst=X1/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xce},
|
|
{name: "src=X6/dst=X2/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd6},
|
|
{name: "src=X6/dst=X3/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde},
|
|
{name: "src=X6/dst=X4/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6},
|
|
{name: "src=X6/dst=X5/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee},
|
|
{name: "src=X6/dst=X6/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6},
|
|
{name: "src=X6/dst=X7/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe},
|
|
{name: "src=X6/dst=X8/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6},
|
|
{name: "src=X6/dst=X9/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce},
|
|
{name: "src=X6/dst=X10/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd6},
|
|
{name: "src=X6/dst=X11/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xde},
|
|
{name: "src=X6/dst=X12/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe6},
|
|
{name: "src=X6/dst=X13/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee},
|
|
{name: "src=X6/dst=X14/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6},
|
|
{name: "src=X6/dst=X15/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe},
|
|
{name: "src=X7/dst=X0/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7},
|
|
{name: "src=X7/dst=X1/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcf},
|
|
{name: "src=X7/dst=X2/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd7},
|
|
{name: "src=X7/dst=X3/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf},
|
|
{name: "src=X7/dst=X4/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7},
|
|
{name: "src=X7/dst=X5/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef},
|
|
{name: "src=X7/dst=X6/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7},
|
|
{name: "src=X7/dst=X7/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff},
|
|
{name: "src=X7/dst=X8/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7},
|
|
{name: "src=X7/dst=X9/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf},
|
|
{name: "src=X7/dst=X10/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd7},
|
|
{name: "src=X7/dst=X11/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdf},
|
|
{name: "src=X7/dst=X12/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe7},
|
|
{name: "src=X7/dst=X13/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef},
|
|
{name: "src=X7/dst=X14/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7},
|
|
{name: "src=X7/dst=X15/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff},
|
|
{name: "src=X8/dst=X0/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0},
|
|
{name: "src=X8/dst=X1/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc8},
|
|
{name: "src=X8/dst=X2/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd0},
|
|
{name: "src=X8/dst=X3/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8},
|
|
{name: "src=X8/dst=X4/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0},
|
|
{name: "src=X8/dst=X5/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8},
|
|
{name: "src=X8/dst=X6/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0},
|
|
{name: "src=X8/dst=X7/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8},
|
|
{name: "src=X8/dst=X8/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0},
|
|
{name: "src=X8/dst=X9/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8},
|
|
{name: "src=X8/dst=X10/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd0},
|
|
{name: "src=X8/dst=X11/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd8},
|
|
{name: "src=X8/dst=X12/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe0},
|
|
{name: "src=X8/dst=X13/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8},
|
|
{name: "src=X8/dst=X14/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0},
|
|
{name: "src=X8/dst=X15/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8},
|
|
{name: "src=X9/dst=X0/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1},
|
|
{name: "src=X9/dst=X1/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc9},
|
|
{name: "src=X9/dst=X2/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd1},
|
|
{name: "src=X9/dst=X3/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9},
|
|
{name: "src=X9/dst=X4/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1},
|
|
{name: "src=X9/dst=X5/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9},
|
|
{name: "src=X9/dst=X6/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1},
|
|
{name: "src=X9/dst=X7/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9},
|
|
{name: "src=X9/dst=X8/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1},
|
|
{name: "src=X9/dst=X9/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9},
|
|
{name: "src=X9/dst=X10/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd1},
|
|
{name: "src=X9/dst=X11/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd9},
|
|
{name: "src=X9/dst=X12/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe1},
|
|
{name: "src=X9/dst=X13/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9},
|
|
{name: "src=X9/dst=X14/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1},
|
|
{name: "src=X9/dst=X15/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9},
|
|
{name: "src=X10/dst=X0/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc2},
|
|
{name: "src=X10/dst=X1/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xca},
|
|
{name: "src=X10/dst=X2/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd2},
|
|
{name: "src=X10/dst=X3/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xda},
|
|
{name: "src=X10/dst=X4/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe2},
|
|
{name: "src=X10/dst=X5/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xea},
|
|
{name: "src=X10/dst=X6/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf2},
|
|
{name: "src=X10/dst=X7/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfa},
|
|
{name: "src=X10/dst=X8/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc2},
|
|
{name: "src=X10/dst=X9/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xca},
|
|
{name: "src=X10/dst=X10/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd2},
|
|
{name: "src=X10/dst=X11/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xda},
|
|
{name: "src=X10/dst=X12/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe2},
|
|
{name: "src=X10/dst=X13/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xea},
|
|
{name: "src=X10/dst=X14/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf2},
|
|
{name: "src=X10/dst=X15/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfa},
|
|
{name: "src=X11/dst=X0/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc3},
|
|
{name: "src=X11/dst=X1/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcb},
|
|
{name: "src=X11/dst=X2/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd3},
|
|
{name: "src=X11/dst=X3/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdb},
|
|
{name: "src=X11/dst=X4/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe3},
|
|
{name: "src=X11/dst=X5/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xeb},
|
|
{name: "src=X11/dst=X6/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf3},
|
|
{name: "src=X11/dst=X7/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfb},
|
|
{name: "src=X11/dst=X8/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc3},
|
|
{name: "src=X11/dst=X9/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcb},
|
|
{name: "src=X11/dst=X10/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd3},
|
|
{name: "src=X11/dst=X11/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdb},
|
|
{name: "src=X11/dst=X12/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe3},
|
|
{name: "src=X11/dst=X13/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xeb},
|
|
{name: "src=X11/dst=X14/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf3},
|
|
{name: "src=X11/dst=X15/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfb},
|
|
{name: "src=X12/dst=X0/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc4},
|
|
{name: "src=X12/dst=X1/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcc},
|
|
{name: "src=X12/dst=X2/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd4},
|
|
{name: "src=X12/dst=X3/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdc},
|
|
{name: "src=X12/dst=X4/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe4},
|
|
{name: "src=X12/dst=X5/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xec},
|
|
{name: "src=X12/dst=X6/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf4},
|
|
{name: "src=X12/dst=X7/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfc},
|
|
{name: "src=X12/dst=X8/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc4},
|
|
{name: "src=X12/dst=X9/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcc},
|
|
{name: "src=X12/dst=X10/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd4},
|
|
{name: "src=X12/dst=X11/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdc},
|
|
{name: "src=X12/dst=X12/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe4},
|
|
{name: "src=X12/dst=X13/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xec},
|
|
{name: "src=X12/dst=X14/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf4},
|
|
{name: "src=X12/dst=X15/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfc},
|
|
{name: "src=X13/dst=X0/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5},
|
|
{name: "src=X13/dst=X1/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcd},
|
|
{name: "src=X13/dst=X2/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd5},
|
|
{name: "src=X13/dst=X3/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd},
|
|
{name: "src=X13/dst=X4/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5},
|
|
{name: "src=X13/dst=X5/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed},
|
|
{name: "src=X13/dst=X6/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5},
|
|
{name: "src=X13/dst=X7/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd},
|
|
{name: "src=X13/dst=X8/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5},
|
|
{name: "src=X13/dst=X9/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd},
|
|
{name: "src=X13/dst=X10/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd5},
|
|
{name: "src=X13/dst=X11/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdd},
|
|
{name: "src=X13/dst=X12/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe5},
|
|
{name: "src=X13/dst=X13/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed},
|
|
{name: "src=X13/dst=X14/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5},
|
|
{name: "src=X13/dst=X15/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd},
|
|
{name: "src=X14/dst=X0/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6},
|
|
{name: "src=X14/dst=X1/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xce},
|
|
{name: "src=X14/dst=X2/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd6},
|
|
{name: "src=X14/dst=X3/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde},
|
|
{name: "src=X14/dst=X4/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6},
|
|
{name: "src=X14/dst=X5/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee},
|
|
{name: "src=X14/dst=X6/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6},
|
|
{name: "src=X14/dst=X7/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe},
|
|
{name: "src=X14/dst=X8/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6},
|
|
{name: "src=X14/dst=X9/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce},
|
|
{name: "src=X14/dst=X10/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd6},
|
|
{name: "src=X14/dst=X11/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xde},
|
|
{name: "src=X14/dst=X12/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe6},
|
|
{name: "src=X14/dst=X13/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee},
|
|
{name: "src=X14/dst=X14/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6},
|
|
{name: "src=X14/dst=X15/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe},
|
|
{name: "src=X15/dst=X0/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7},
|
|
{name: "src=X15/dst=X1/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcf},
|
|
{name: "src=X15/dst=X2/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd7},
|
|
{name: "src=X15/dst=X3/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf},
|
|
{name: "src=X15/dst=X4/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7},
|
|
{name: "src=X15/dst=X5/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef},
|
|
{name: "src=X15/dst=X6/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7},
|
|
{name: "src=X15/dst=X7/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff},
|
|
{name: "src=X15/dst=X8/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7},
|
|
{name: "src=X15/dst=X9/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf},
|
|
{name: "src=X15/dst=X10/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd7},
|
|
{name: "src=X15/dst=X11/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdf},
|
|
{name: "src=X15/dst=X12/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe7},
|
|
{name: "src=X15/dst=X13/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef},
|
|
{name: "src=X15/dst=X14/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7},
|
|
{name: "src=X15/dst=X15/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff},
|
|
{name: "src=X0/dst=AX/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0},
|
|
{name: "src=X0/dst=BX/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8},
|
|
{name: "src=X0/dst=SP/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0},
|
|
{name: "src=X0/dst=BP/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8},
|
|
{name: "src=X0/dst=SI/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0},
|
|
{name: "src=X0/dst=DI/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8},
|
|
{name: "src=X0/dst=R8/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0},
|
|
{name: "src=X0/dst=R9/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8},
|
|
{name: "src=X0/dst=R13/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8},
|
|
{name: "src=X0/dst=R14/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0},
|
|
{name: "src=X0/dst=R15/srcOnModRMReg=false", srcReg: RegX0, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8},
|
|
{name: "src=X1/dst=AX/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc1},
|
|
{name: "src=X1/dst=BX/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd9},
|
|
{name: "src=X1/dst=SP/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe1},
|
|
{name: "src=X1/dst=BP/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe9},
|
|
{name: "src=X1/dst=SI/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf1},
|
|
{name: "src=X1/dst=DI/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf9},
|
|
{name: "src=X1/dst=R8/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc1},
|
|
{name: "src=X1/dst=R9/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc9},
|
|
{name: "src=X1/dst=R13/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe9},
|
|
{name: "src=X1/dst=R14/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf1},
|
|
{name: "src=X1/dst=R15/srcOnModRMReg=false", srcReg: RegX1, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf9},
|
|
{name: "src=X2/dst=AX/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc2},
|
|
{name: "src=X2/dst=BX/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xda},
|
|
{name: "src=X2/dst=SP/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe2},
|
|
{name: "src=X2/dst=BP/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xea},
|
|
{name: "src=X2/dst=SI/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf2},
|
|
{name: "src=X2/dst=DI/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfa},
|
|
{name: "src=X2/dst=R8/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc2},
|
|
{name: "src=X2/dst=R9/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xca},
|
|
{name: "src=X2/dst=R13/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xea},
|
|
{name: "src=X2/dst=R14/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf2},
|
|
{name: "src=X2/dst=R15/srcOnModRMReg=false", srcReg: RegX2, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfa},
|
|
{name: "src=X3/dst=AX/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3},
|
|
{name: "src=X3/dst=BX/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb},
|
|
{name: "src=X3/dst=SP/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3},
|
|
{name: "src=X3/dst=BP/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb},
|
|
{name: "src=X3/dst=SI/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3},
|
|
{name: "src=X3/dst=DI/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb},
|
|
{name: "src=X3/dst=R8/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3},
|
|
{name: "src=X3/dst=R9/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb},
|
|
{name: "src=X3/dst=R13/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb},
|
|
{name: "src=X3/dst=R14/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3},
|
|
{name: "src=X3/dst=R15/srcOnModRMReg=false", srcReg: RegX3, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb},
|
|
{name: "src=X4/dst=AX/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4},
|
|
{name: "src=X4/dst=BX/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc},
|
|
{name: "src=X4/dst=SP/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4},
|
|
{name: "src=X4/dst=BP/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec},
|
|
{name: "src=X4/dst=SI/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4},
|
|
{name: "src=X4/dst=DI/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc},
|
|
{name: "src=X4/dst=R8/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4},
|
|
{name: "src=X4/dst=R9/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc},
|
|
{name: "src=X4/dst=R13/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec},
|
|
{name: "src=X4/dst=R14/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4},
|
|
{name: "src=X4/dst=R15/srcOnModRMReg=false", srcReg: RegX4, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc},
|
|
{name: "src=X5/dst=AX/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5},
|
|
{name: "src=X5/dst=BX/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd},
|
|
{name: "src=X5/dst=SP/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5},
|
|
{name: "src=X5/dst=BP/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed},
|
|
{name: "src=X5/dst=SI/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5},
|
|
{name: "src=X5/dst=DI/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd},
|
|
{name: "src=X5/dst=R8/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5},
|
|
{name: "src=X5/dst=R9/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd},
|
|
{name: "src=X5/dst=R13/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed},
|
|
{name: "src=X5/dst=R14/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5},
|
|
{name: "src=X5/dst=R15/srcOnModRMReg=false", srcReg: RegX5, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd},
|
|
{name: "src=X6/dst=AX/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6},
|
|
{name: "src=X6/dst=BX/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde},
|
|
{name: "src=X6/dst=SP/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6},
|
|
{name: "src=X6/dst=BP/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee},
|
|
{name: "src=X6/dst=SI/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6},
|
|
{name: "src=X6/dst=DI/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe},
|
|
{name: "src=X6/dst=R8/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6},
|
|
{name: "src=X6/dst=R9/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce},
|
|
{name: "src=X6/dst=R13/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee},
|
|
{name: "src=X6/dst=R14/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6},
|
|
{name: "src=X6/dst=R15/srcOnModRMReg=false", srcReg: RegX6, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe},
|
|
{name: "src=X7/dst=AX/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7},
|
|
{name: "src=X7/dst=BX/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf},
|
|
{name: "src=X7/dst=SP/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7},
|
|
{name: "src=X7/dst=BP/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef},
|
|
{name: "src=X7/dst=SI/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7},
|
|
{name: "src=X7/dst=DI/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff},
|
|
{name: "src=X7/dst=R8/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7},
|
|
{name: "src=X7/dst=R9/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf},
|
|
{name: "src=X7/dst=R13/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef},
|
|
{name: "src=X7/dst=R14/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7},
|
|
{name: "src=X7/dst=R15/srcOnModRMReg=false", srcReg: RegX7, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff},
|
|
{name: "src=X8/dst=AX/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0},
|
|
{name: "src=X8/dst=BX/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8},
|
|
{name: "src=X8/dst=SP/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0},
|
|
{name: "src=X8/dst=BP/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8},
|
|
{name: "src=X8/dst=SI/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0},
|
|
{name: "src=X8/dst=DI/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8},
|
|
{name: "src=X8/dst=R8/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0},
|
|
{name: "src=X8/dst=R9/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8},
|
|
{name: "src=X8/dst=R13/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8},
|
|
{name: "src=X8/dst=R14/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0},
|
|
{name: "src=X8/dst=R15/srcOnModRMReg=false", srcReg: RegX8, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8},
|
|
{name: "src=X9/dst=AX/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1},
|
|
{name: "src=X9/dst=BX/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9},
|
|
{name: "src=X9/dst=SP/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1},
|
|
{name: "src=X9/dst=BP/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9},
|
|
{name: "src=X9/dst=SI/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1},
|
|
{name: "src=X9/dst=DI/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9},
|
|
{name: "src=X9/dst=R8/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1},
|
|
{name: "src=X9/dst=R9/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9},
|
|
{name: "src=X9/dst=R13/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9},
|
|
{name: "src=X9/dst=R14/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1},
|
|
{name: "src=X9/dst=R15/srcOnModRMReg=false", srcReg: RegX9, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9},
|
|
{name: "src=X10/dst=AX/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc2},
|
|
{name: "src=X10/dst=BX/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xda},
|
|
{name: "src=X10/dst=SP/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe2},
|
|
{name: "src=X10/dst=BP/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xea},
|
|
{name: "src=X10/dst=SI/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf2},
|
|
{name: "src=X10/dst=DI/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfa},
|
|
{name: "src=X10/dst=R8/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc2},
|
|
{name: "src=X10/dst=R9/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xca},
|
|
{name: "src=X10/dst=R13/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xea},
|
|
{name: "src=X10/dst=R14/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf2},
|
|
{name: "src=X10/dst=R15/srcOnModRMReg=false", srcReg: RegX10, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfa},
|
|
{name: "src=X11/dst=AX/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc3},
|
|
{name: "src=X11/dst=BX/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdb},
|
|
{name: "src=X11/dst=SP/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe3},
|
|
{name: "src=X11/dst=BP/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xeb},
|
|
{name: "src=X11/dst=SI/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf3},
|
|
{name: "src=X11/dst=DI/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfb},
|
|
{name: "src=X11/dst=R8/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc3},
|
|
{name: "src=X11/dst=R9/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcb},
|
|
{name: "src=X11/dst=R13/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xeb},
|
|
{name: "src=X11/dst=R14/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf3},
|
|
{name: "src=X11/dst=R15/srcOnModRMReg=false", srcReg: RegX11, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfb},
|
|
{name: "src=X12/dst=AX/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc4},
|
|
{name: "src=X12/dst=BX/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdc},
|
|
{name: "src=X12/dst=SP/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe4},
|
|
{name: "src=X12/dst=BP/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xec},
|
|
{name: "src=X12/dst=SI/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf4},
|
|
{name: "src=X12/dst=DI/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfc},
|
|
{name: "src=X12/dst=R8/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc4},
|
|
{name: "src=X12/dst=R9/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcc},
|
|
{name: "src=X12/dst=R13/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xec},
|
|
{name: "src=X12/dst=R14/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf4},
|
|
{name: "src=X12/dst=R15/srcOnModRMReg=false", srcReg: RegX12, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfc},
|
|
{name: "src=X13/dst=AX/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5},
|
|
{name: "src=X13/dst=BX/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd},
|
|
{name: "src=X13/dst=SP/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5},
|
|
{name: "src=X13/dst=BP/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed},
|
|
{name: "src=X13/dst=SI/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5},
|
|
{name: "src=X13/dst=DI/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd},
|
|
{name: "src=X13/dst=R8/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5},
|
|
{name: "src=X13/dst=R9/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd},
|
|
{name: "src=X13/dst=R13/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed},
|
|
{name: "src=X13/dst=R14/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5},
|
|
{name: "src=X13/dst=R15/srcOnModRMReg=false", srcReg: RegX13, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd},
|
|
{name: "src=X14/dst=AX/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6},
|
|
{name: "src=X14/dst=BX/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde},
|
|
{name: "src=X14/dst=SP/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6},
|
|
{name: "src=X14/dst=BP/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee},
|
|
{name: "src=X14/dst=SI/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6},
|
|
{name: "src=X14/dst=DI/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe},
|
|
{name: "src=X14/dst=R8/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6},
|
|
{name: "src=X14/dst=R9/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce},
|
|
{name: "src=X14/dst=R13/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee},
|
|
{name: "src=X14/dst=R14/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6},
|
|
{name: "src=X14/dst=R15/srcOnModRMReg=false", srcReg: RegX14, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe},
|
|
{name: "src=X15/dst=AX/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegAX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7},
|
|
{name: "src=X15/dst=BX/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegBX, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf},
|
|
{name: "src=X15/dst=SP/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegSP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7},
|
|
{name: "src=X15/dst=BP/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegBP, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef},
|
|
{name: "src=X15/dst=SI/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegSI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7},
|
|
{name: "src=X15/dst=DI/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegDI, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff},
|
|
{name: "src=X15/dst=R8/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7},
|
|
{name: "src=X15/dst=R9/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf},
|
|
{name: "src=X15/dst=R13/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef},
|
|
{name: "src=X15/dst=R14/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7},
|
|
{name: "src=X15/dst=R15/srcOnModRMReg=false", srcReg: RegX15, dstReg: RegR15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff},
|
|
{name: "src=AX/dst=X0/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc0},
|
|
{name: "src=AX/dst=X1/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc8},
|
|
{name: "src=AX/dst=X2/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd0},
|
|
{name: "src=AX/dst=X3/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd8},
|
|
{name: "src=AX/dst=X4/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe0},
|
|
{name: "src=AX/dst=X5/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe8},
|
|
{name: "src=AX/dst=X6/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf0},
|
|
{name: "src=AX/dst=X7/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf8},
|
|
{name: "src=AX/dst=X8/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc0},
|
|
{name: "src=AX/dst=X9/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc8},
|
|
{name: "src=AX/dst=X10/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd0},
|
|
{name: "src=AX/dst=X11/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd8},
|
|
{name: "src=AX/dst=X12/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe0},
|
|
{name: "src=AX/dst=X13/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe8},
|
|
{name: "src=AX/dst=X14/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf0},
|
|
{name: "src=AX/dst=X15/srcOnModRMReg=false", srcReg: RegAX, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf8},
|
|
{name: "src=BX/dst=X0/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc3},
|
|
{name: "src=BX/dst=X1/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcb},
|
|
{name: "src=BX/dst=X2/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd3},
|
|
{name: "src=BX/dst=X3/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdb},
|
|
{name: "src=BX/dst=X4/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe3},
|
|
{name: "src=BX/dst=X5/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xeb},
|
|
{name: "src=BX/dst=X6/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf3},
|
|
{name: "src=BX/dst=X7/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfb},
|
|
{name: "src=BX/dst=X8/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc3},
|
|
{name: "src=BX/dst=X9/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcb},
|
|
{name: "src=BX/dst=X10/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd3},
|
|
{name: "src=BX/dst=X11/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdb},
|
|
{name: "src=BX/dst=X12/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe3},
|
|
{name: "src=BX/dst=X13/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xeb},
|
|
{name: "src=BX/dst=X14/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf3},
|
|
{name: "src=BX/dst=X15/srcOnModRMReg=false", srcReg: RegBX, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfb},
|
|
{name: "src=SP/dst=X0/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc4},
|
|
{name: "src=SP/dst=X1/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcc},
|
|
{name: "src=SP/dst=X2/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd4},
|
|
{name: "src=SP/dst=X3/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdc},
|
|
{name: "src=SP/dst=X4/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe4},
|
|
{name: "src=SP/dst=X5/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xec},
|
|
{name: "src=SP/dst=X6/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf4},
|
|
{name: "src=SP/dst=X7/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfc},
|
|
{name: "src=SP/dst=X8/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc4},
|
|
{name: "src=SP/dst=X9/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcc},
|
|
{name: "src=SP/dst=X10/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd4},
|
|
{name: "src=SP/dst=X11/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdc},
|
|
{name: "src=SP/dst=X12/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe4},
|
|
{name: "src=SP/dst=X13/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xec},
|
|
{name: "src=SP/dst=X14/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf4},
|
|
{name: "src=SP/dst=X15/srcOnModRMReg=false", srcReg: RegSP, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfc},
|
|
{name: "src=BP/dst=X0/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc5},
|
|
{name: "src=BP/dst=X1/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcd},
|
|
{name: "src=BP/dst=X2/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd5},
|
|
{name: "src=BP/dst=X3/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdd},
|
|
{name: "src=BP/dst=X4/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe5},
|
|
{name: "src=BP/dst=X5/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xed},
|
|
{name: "src=BP/dst=X6/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf5},
|
|
{name: "src=BP/dst=X7/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfd},
|
|
{name: "src=BP/dst=X8/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc5},
|
|
{name: "src=BP/dst=X9/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcd},
|
|
{name: "src=BP/dst=X10/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd5},
|
|
{name: "src=BP/dst=X11/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdd},
|
|
{name: "src=BP/dst=X12/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe5},
|
|
{name: "src=BP/dst=X13/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xed},
|
|
{name: "src=BP/dst=X14/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf5},
|
|
{name: "src=BP/dst=X15/srcOnModRMReg=false", srcReg: RegBP, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfd},
|
|
{name: "src=SI/dst=X0/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc6},
|
|
{name: "src=SI/dst=X1/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xce},
|
|
{name: "src=SI/dst=X2/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd6},
|
|
{name: "src=SI/dst=X3/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xde},
|
|
{name: "src=SI/dst=X4/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe6},
|
|
{name: "src=SI/dst=X5/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xee},
|
|
{name: "src=SI/dst=X6/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf6},
|
|
{name: "src=SI/dst=X7/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xfe},
|
|
{name: "src=SI/dst=X8/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc6},
|
|
{name: "src=SI/dst=X9/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xce},
|
|
{name: "src=SI/dst=X10/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd6},
|
|
{name: "src=SI/dst=X11/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xde},
|
|
{name: "src=SI/dst=X12/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe6},
|
|
{name: "src=SI/dst=X13/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xee},
|
|
{name: "src=SI/dst=X14/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf6},
|
|
{name: "src=SI/dst=X15/srcOnModRMReg=false", srcReg: RegSI, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xfe},
|
|
{name: "src=DI/dst=X0/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xc7},
|
|
{name: "src=DI/dst=X1/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xcf},
|
|
{name: "src=DI/dst=X2/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xd7},
|
|
{name: "src=DI/dst=X3/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xdf},
|
|
{name: "src=DI/dst=X4/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xe7},
|
|
{name: "src=DI/dst=X5/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xef},
|
|
{name: "src=DI/dst=X6/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xf7},
|
|
{name: "src=DI/dst=X7/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x0, expModRM: 0xff},
|
|
{name: "src=DI/dst=X8/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xc7},
|
|
{name: "src=DI/dst=X9/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xcf},
|
|
{name: "src=DI/dst=X10/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xd7},
|
|
{name: "src=DI/dst=X11/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xdf},
|
|
{name: "src=DI/dst=X12/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xe7},
|
|
{name: "src=DI/dst=X13/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xef},
|
|
{name: "src=DI/dst=X14/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xf7},
|
|
{name: "src=DI/dst=X15/srcOnModRMReg=false", srcReg: RegDI, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x44, expModRM: 0xff},
|
|
{name: "src=R8/dst=X0/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc0},
|
|
{name: "src=R8/dst=X1/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc8},
|
|
{name: "src=R8/dst=X2/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd0},
|
|
{name: "src=R8/dst=X3/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd8},
|
|
{name: "src=R8/dst=X4/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe0},
|
|
{name: "src=R8/dst=X5/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe8},
|
|
{name: "src=R8/dst=X6/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf0},
|
|
{name: "src=R8/dst=X7/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf8},
|
|
{name: "src=R8/dst=X8/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc0},
|
|
{name: "src=R8/dst=X9/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc8},
|
|
{name: "src=R8/dst=X10/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd0},
|
|
{name: "src=R8/dst=X11/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd8},
|
|
{name: "src=R8/dst=X12/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe0},
|
|
{name: "src=R8/dst=X13/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe8},
|
|
{name: "src=R8/dst=X14/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf0},
|
|
{name: "src=R8/dst=X15/srcOnModRMReg=false", srcReg: RegR8, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf8},
|
|
{name: "src=R9/dst=X0/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc1},
|
|
{name: "src=R9/dst=X1/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc9},
|
|
{name: "src=R9/dst=X2/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd1},
|
|
{name: "src=R9/dst=X3/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd9},
|
|
{name: "src=R9/dst=X4/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe1},
|
|
{name: "src=R9/dst=X5/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe9},
|
|
{name: "src=R9/dst=X6/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf1},
|
|
{name: "src=R9/dst=X7/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf9},
|
|
{name: "src=R9/dst=X8/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc1},
|
|
{name: "src=R9/dst=X9/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc9},
|
|
{name: "src=R9/dst=X10/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd1},
|
|
{name: "src=R9/dst=X11/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd9},
|
|
{name: "src=R9/dst=X12/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe1},
|
|
{name: "src=R9/dst=X13/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe9},
|
|
{name: "src=R9/dst=X14/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf1},
|
|
{name: "src=R9/dst=X15/srcOnModRMReg=false", srcReg: RegR9, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf9},
|
|
{name: "src=R13/dst=X0/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc5},
|
|
{name: "src=R13/dst=X1/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcd},
|
|
{name: "src=R13/dst=X2/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd5},
|
|
{name: "src=R13/dst=X3/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdd},
|
|
{name: "src=R13/dst=X4/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe5},
|
|
{name: "src=R13/dst=X5/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xed},
|
|
{name: "src=R13/dst=X6/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf5},
|
|
{name: "src=R13/dst=X7/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfd},
|
|
{name: "src=R13/dst=X8/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc5},
|
|
{name: "src=R13/dst=X9/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcd},
|
|
{name: "src=R13/dst=X10/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd5},
|
|
{name: "src=R13/dst=X11/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdd},
|
|
{name: "src=R13/dst=X12/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe5},
|
|
{name: "src=R13/dst=X13/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xed},
|
|
{name: "src=R13/dst=X14/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf5},
|
|
{name: "src=R13/dst=X15/srcOnModRMReg=false", srcReg: RegR13, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfd},
|
|
{name: "src=R14/dst=X0/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc6},
|
|
{name: "src=R14/dst=X1/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xce},
|
|
{name: "src=R14/dst=X2/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd6},
|
|
{name: "src=R14/dst=X3/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xde},
|
|
{name: "src=R14/dst=X4/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe6},
|
|
{name: "src=R14/dst=X5/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xee},
|
|
{name: "src=R14/dst=X6/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf6},
|
|
{name: "src=R14/dst=X7/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xfe},
|
|
{name: "src=R14/dst=X8/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc6},
|
|
{name: "src=R14/dst=X9/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xce},
|
|
{name: "src=R14/dst=X10/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd6},
|
|
{name: "src=R14/dst=X11/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xde},
|
|
{name: "src=R14/dst=X12/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe6},
|
|
{name: "src=R14/dst=X13/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xee},
|
|
{name: "src=R14/dst=X14/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf6},
|
|
{name: "src=R14/dst=X15/srcOnModRMReg=false", srcReg: RegR14, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xfe},
|
|
{name: "src=R15/dst=X0/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX0, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xc7},
|
|
{name: "src=R15/dst=X1/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX1, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xcf},
|
|
{name: "src=R15/dst=X2/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX2, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xd7},
|
|
{name: "src=R15/dst=X3/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX3, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xdf},
|
|
{name: "src=R15/dst=X4/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX4, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xe7},
|
|
{name: "src=R15/dst=X5/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX5, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xef},
|
|
{name: "src=R15/dst=X6/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX6, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xf7},
|
|
{name: "src=R15/dst=X7/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX7, srcOnModRMReg: false, expRexPrefix: 0x41, expModRM: 0xff},
|
|
{name: "src=R15/dst=X8/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX8, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xc7},
|
|
{name: "src=R15/dst=X9/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX9, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xcf},
|
|
{name: "src=R15/dst=X10/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX10, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xd7},
|
|
{name: "src=R15/dst=X11/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX11, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xdf},
|
|
{name: "src=R15/dst=X12/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX12, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xe7},
|
|
{name: "src=R15/dst=X13/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX13, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xef},
|
|
{name: "src=R15/dst=X14/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX14, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xf7},
|
|
{name: "src=R15/dst=X15/srcOnModRMReg=false", srcReg: RegR15, dstReg: RegX15, srcOnModRMReg: false, expRexPrefix: 0x45, expModRM: 0xff},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
n := nodeImpl{srcReg: tc.srcReg, dstReg: tc.dstReg}
|
|
rexPrefix, modRM, err := n.getRegisterToRegisterModRM(tc.srcOnModRMReg)
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.expRexPrefix, rexPrefix, tc.name)
|
|
require.Equal(t, tc.expModRM, modRM, tc.name)
|
|
}
|
|
}
|