329ccca6b1
This switches to gofumpt and applies changes, as I've noticed working in dapr (who uses this) that it finds some things that are annoying, such as inconsistent block formatting in test tables. Signed-off-by: Adrian Cole <adrian@tetrate.io>
1266 lines
141 KiB
Go
1266 lines
141 KiB
Go
package amd64
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import (
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"testing"
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"github.com/tetratelabs/wazero/internal/asm"
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"github.com/tetratelabs/wazero/internal/testing/require"
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)
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/*
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var cs []string
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cs = append(cs, fmt.Sprintf(
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`{name: "%s", inst: %s, dst: Reg%s, exp: %#v}`,
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fmt.Sprintf("inst=%s/reg=%s", InstructionName(inst), RegisterName(reg)),
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InstructionName(inst), RegisterName(reg),
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a.buf.Bytes(),
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))
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fmt.Println(strings.Join(cs, ",\n"))
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*/
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func TestAssemblerImpl_EncodeNoneToRegister(t *testing.T) {
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t.Run("error", func(t *testing.T) {
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a := NewAssembler()
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err := a.encodeNoneToRegister(&nodeImpl{
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instruction: ADDL,
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types: operandTypesNoneToRegister, dstReg: RegAX,
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})
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require.Error(t, err)
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t.Run("error", func(t *testing.T) {
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tests := []struct {
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n *nodeImpl
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expErr string
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}{
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{
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n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToRegister, dstReg: RegAX},
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expErr: "ADDL is unsupported for from:none,to:register type",
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},
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{
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n: &nodeImpl{instruction: JMP, types: operandTypesNoneToRegister},
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expErr: "invalid register [nil]",
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},
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}
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for _, tt := range tests {
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a := NewAssembler()
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err := a.encodeNoneToRegister(tt.n)
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require.EqualError(t, err, tt.expErr, tt.expErr)
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}
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})
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})
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tests := []struct {
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name string
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inst asm.Instruction
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dst asm.Register
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exp []byte
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}{
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{name: "inst=JMP/reg=AX", inst: JMP, dst: RegAX, exp: []byte{0xff, 0xe0}},
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{name: "inst=JMP/reg=BX", inst: JMP, dst: RegBX, exp: []byte{0xff, 0xe3}},
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{name: "inst=JMP/reg=SP", inst: JMP, dst: RegSP, exp: []byte{0xff, 0xe4}},
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{name: "inst=JMP/reg=BP", inst: JMP, dst: RegBP, exp: []byte{0xff, 0xe5}},
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{name: "inst=JMP/reg=SI", inst: JMP, dst: RegSI, exp: []byte{0xff, 0xe6}},
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{name: "inst=JMP/reg=DI", inst: JMP, dst: RegDI, exp: []byte{0xff, 0xe7}},
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{name: "inst=JMP/reg=R8", inst: JMP, dst: RegR8, exp: []byte{0x41, 0xff, 0xe0}},
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{name: "inst=JMP/reg=R9", inst: JMP, dst: RegR9, exp: []byte{0x41, 0xff, 0xe1}},
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{name: "inst=JMP/reg=R13", inst: JMP, dst: RegR13, exp: []byte{0x41, 0xff, 0xe5}},
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{name: "inst=JMP/reg=R14", inst: JMP, dst: RegR14, exp: []byte{0x41, 0xff, 0xe6}},
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{name: "inst=JMP/reg=R15", inst: JMP, dst: RegR15, exp: []byte{0x41, 0xff, 0xe7}},
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{name: "inst=SETCC/reg=AX", inst: SETCC, dst: RegAX, exp: []byte{0xf, 0x93, 0xc0}},
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{name: "inst=SETCC/reg=BX", inst: SETCC, dst: RegBX, exp: []byte{0xf, 0x93, 0xc3}},
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{name: "inst=SETCC/reg=SP", inst: SETCC, dst: RegSP, exp: []byte{0x40, 0xf, 0x93, 0xc4}},
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{name: "inst=SETCC/reg=BP", inst: SETCC, dst: RegBP, exp: []byte{0x40, 0xf, 0x93, 0xc5}},
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{name: "inst=SETCC/reg=SI", inst: SETCC, dst: RegSI, exp: []byte{0x40, 0xf, 0x93, 0xc6}},
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{name: "inst=SETCC/reg=DI", inst: SETCC, dst: RegDI, exp: []byte{0x40, 0xf, 0x93, 0xc7}},
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{name: "inst=SETCC/reg=R8", inst: SETCC, dst: RegR8, exp: []byte{0x41, 0xf, 0x93, 0xc0}},
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{name: "inst=SETCC/reg=R9", inst: SETCC, dst: RegR9, exp: []byte{0x41, 0xf, 0x93, 0xc1}},
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{name: "inst=SETCC/reg=R13", inst: SETCC, dst: RegR13, exp: []byte{0x41, 0xf, 0x93, 0xc5}},
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{name: "inst=SETCC/reg=R14", inst: SETCC, dst: RegR14, exp: []byte{0x41, 0xf, 0x93, 0xc6}},
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{name: "inst=SETCC/reg=R15", inst: SETCC, dst: RegR15, exp: []byte{0x41, 0xf, 0x93, 0xc7}},
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{name: "inst=SETCS/reg=AX", inst: SETCS, dst: RegAX, exp: []byte{0xf, 0x92, 0xc0}},
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{name: "inst=SETCS/reg=BX", inst: SETCS, dst: RegBX, exp: []byte{0xf, 0x92, 0xc3}},
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{name: "inst=SETCS/reg=SP", inst: SETCS, dst: RegSP, exp: []byte{0x40, 0xf, 0x92, 0xc4}},
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{name: "inst=SETCS/reg=BP", inst: SETCS, dst: RegBP, exp: []byte{0x40, 0xf, 0x92, 0xc5}},
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{name: "inst=SETCS/reg=SI", inst: SETCS, dst: RegSI, exp: []byte{0x40, 0xf, 0x92, 0xc6}},
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{name: "inst=SETCS/reg=DI", inst: SETCS, dst: RegDI, exp: []byte{0x40, 0xf, 0x92, 0xc7}},
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{name: "inst=SETCS/reg=R8", inst: SETCS, dst: RegR8, exp: []byte{0x41, 0xf, 0x92, 0xc0}},
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{name: "inst=SETCS/reg=R9", inst: SETCS, dst: RegR9, exp: []byte{0x41, 0xf, 0x92, 0xc1}},
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{name: "inst=SETCS/reg=R13", inst: SETCS, dst: RegR13, exp: []byte{0x41, 0xf, 0x92, 0xc5}},
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{name: "inst=SETCS/reg=R14", inst: SETCS, dst: RegR14, exp: []byte{0x41, 0xf, 0x92, 0xc6}},
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{name: "inst=SETCS/reg=R15", inst: SETCS, dst: RegR15, exp: []byte{0x41, 0xf, 0x92, 0xc7}},
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{name: "inst=SETEQ/reg=AX", inst: SETEQ, dst: RegAX, exp: []byte{0xf, 0x94, 0xc0}},
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{name: "inst=SETEQ/reg=BX", inst: SETEQ, dst: RegBX, exp: []byte{0xf, 0x94, 0xc3}},
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{name: "inst=SETEQ/reg=SP", inst: SETEQ, dst: RegSP, exp: []byte{0x40, 0xf, 0x94, 0xc4}},
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{name: "inst=SETEQ/reg=BP", inst: SETEQ, dst: RegBP, exp: []byte{0x40, 0xf, 0x94, 0xc5}},
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{name: "inst=SETEQ/reg=SI", inst: SETEQ, dst: RegSI, exp: []byte{0x40, 0xf, 0x94, 0xc6}},
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{name: "inst=SETEQ/reg=DI", inst: SETEQ, dst: RegDI, exp: []byte{0x40, 0xf, 0x94, 0xc7}},
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{name: "inst=SETEQ/reg=R8", inst: SETEQ, dst: RegR8, exp: []byte{0x41, 0xf, 0x94, 0xc0}},
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{name: "inst=SETEQ/reg=R9", inst: SETEQ, dst: RegR9, exp: []byte{0x41, 0xf, 0x94, 0xc1}},
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{name: "inst=SETEQ/reg=R13", inst: SETEQ, dst: RegR13, exp: []byte{0x41, 0xf, 0x94, 0xc5}},
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{name: "inst=SETEQ/reg=R14", inst: SETEQ, dst: RegR14, exp: []byte{0x41, 0xf, 0x94, 0xc6}},
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{name: "inst=SETEQ/reg=R15", inst: SETEQ, dst: RegR15, exp: []byte{0x41, 0xf, 0x94, 0xc7}},
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{name: "inst=SETGE/reg=AX", inst: SETGE, dst: RegAX, exp: []byte{0xf, 0x9d, 0xc0}},
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{name: "inst=SETGE/reg=BX", inst: SETGE, dst: RegBX, exp: []byte{0xf, 0x9d, 0xc3}},
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{name: "inst=SETGE/reg=SP", inst: SETGE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9d, 0xc4}},
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{name: "inst=SETGE/reg=BP", inst: SETGE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9d, 0xc5}},
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{name: "inst=SETGE/reg=SI", inst: SETGE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9d, 0xc6}},
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{name: "inst=SETGE/reg=DI", inst: SETGE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9d, 0xc7}},
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{name: "inst=SETGE/reg=R8", inst: SETGE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9d, 0xc0}},
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{name: "inst=SETGE/reg=R9", inst: SETGE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9d, 0xc1}},
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{name: "inst=SETGE/reg=R13", inst: SETGE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9d, 0xc5}},
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{name: "inst=SETGE/reg=R14", inst: SETGE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9d, 0xc6}},
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{name: "inst=SETGE/reg=R15", inst: SETGE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9d, 0xc7}},
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{name: "inst=SETGT/reg=AX", inst: SETGT, dst: RegAX, exp: []byte{0xf, 0x9f, 0xc0}},
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{name: "inst=SETGT/reg=BX", inst: SETGT, dst: RegBX, exp: []byte{0xf, 0x9f, 0xc3}},
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{name: "inst=SETGT/reg=SP", inst: SETGT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9f, 0xc4}},
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{name: "inst=SETGT/reg=BP", inst: SETGT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9f, 0xc5}},
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{name: "inst=SETGT/reg=SI", inst: SETGT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9f, 0xc6}},
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{name: "inst=SETGT/reg=DI", inst: SETGT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9f, 0xc7}},
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{name: "inst=SETGT/reg=R8", inst: SETGT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9f, 0xc0}},
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{name: "inst=SETGT/reg=R9", inst: SETGT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9f, 0xc1}},
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{name: "inst=SETGT/reg=R13", inst: SETGT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9f, 0xc5}},
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{name: "inst=SETGT/reg=R14", inst: SETGT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9f, 0xc6}},
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{name: "inst=SETGT/reg=R15", inst: SETGT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9f, 0xc7}},
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{name: "inst=SETHI/reg=AX", inst: SETHI, dst: RegAX, exp: []byte{0xf, 0x97, 0xc0}},
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{name: "inst=SETHI/reg=BX", inst: SETHI, dst: RegBX, exp: []byte{0xf, 0x97, 0xc3}},
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{name: "inst=SETHI/reg=SP", inst: SETHI, dst: RegSP, exp: []byte{0x40, 0xf, 0x97, 0xc4}},
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{name: "inst=SETHI/reg=BP", inst: SETHI, dst: RegBP, exp: []byte{0x40, 0xf, 0x97, 0xc5}},
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{name: "inst=SETHI/reg=SI", inst: SETHI, dst: RegSI, exp: []byte{0x40, 0xf, 0x97, 0xc6}},
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{name: "inst=SETHI/reg=DI", inst: SETHI, dst: RegDI, exp: []byte{0x40, 0xf, 0x97, 0xc7}},
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{name: "inst=SETHI/reg=R8", inst: SETHI, dst: RegR8, exp: []byte{0x41, 0xf, 0x97, 0xc0}},
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{name: "inst=SETHI/reg=R9", inst: SETHI, dst: RegR9, exp: []byte{0x41, 0xf, 0x97, 0xc1}},
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{name: "inst=SETHI/reg=R13", inst: SETHI, dst: RegR13, exp: []byte{0x41, 0xf, 0x97, 0xc5}},
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{name: "inst=SETHI/reg=R14", inst: SETHI, dst: RegR14, exp: []byte{0x41, 0xf, 0x97, 0xc6}},
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{name: "inst=SETHI/reg=R15", inst: SETHI, dst: RegR15, exp: []byte{0x41, 0xf, 0x97, 0xc7}},
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{name: "inst=SETLE/reg=AX", inst: SETLE, dst: RegAX, exp: []byte{0xf, 0x9e, 0xc0}},
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{name: "inst=SETLE/reg=BX", inst: SETLE, dst: RegBX, exp: []byte{0xf, 0x9e, 0xc3}},
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{name: "inst=SETLE/reg=SP", inst: SETLE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9e, 0xc4}},
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{name: "inst=SETLE/reg=BP", inst: SETLE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9e, 0xc5}},
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{name: "inst=SETLE/reg=SI", inst: SETLE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9e, 0xc6}},
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{name: "inst=SETLE/reg=DI", inst: SETLE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9e, 0xc7}},
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{name: "inst=SETLE/reg=R8", inst: SETLE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9e, 0xc0}},
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{name: "inst=SETLE/reg=R9", inst: SETLE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9e, 0xc1}},
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{name: "inst=SETLE/reg=R13", inst: SETLE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9e, 0xc5}},
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{name: "inst=SETLE/reg=R14", inst: SETLE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9e, 0xc6}},
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{name: "inst=SETLE/reg=R15", inst: SETLE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9e, 0xc7}},
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{name: "inst=SETLS/reg=AX", inst: SETLS, dst: RegAX, exp: []byte{0xf, 0x96, 0xc0}},
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{name: "inst=SETLS/reg=BX", inst: SETLS, dst: RegBX, exp: []byte{0xf, 0x96, 0xc3}},
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{name: "inst=SETLS/reg=SP", inst: SETLS, dst: RegSP, exp: []byte{0x40, 0xf, 0x96, 0xc4}},
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{name: "inst=SETLS/reg=BP", inst: SETLS, dst: RegBP, exp: []byte{0x40, 0xf, 0x96, 0xc5}},
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{name: "inst=SETLS/reg=SI", inst: SETLS, dst: RegSI, exp: []byte{0x40, 0xf, 0x96, 0xc6}},
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{name: "inst=SETLS/reg=DI", inst: SETLS, dst: RegDI, exp: []byte{0x40, 0xf, 0x96, 0xc7}},
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{name: "inst=SETLS/reg=R8", inst: SETLS, dst: RegR8, exp: []byte{0x41, 0xf, 0x96, 0xc0}},
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{name: "inst=SETLS/reg=R9", inst: SETLS, dst: RegR9, exp: []byte{0x41, 0xf, 0x96, 0xc1}},
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{name: "inst=SETLS/reg=R13", inst: SETLS, dst: RegR13, exp: []byte{0x41, 0xf, 0x96, 0xc5}},
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{name: "inst=SETLS/reg=R14", inst: SETLS, dst: RegR14, exp: []byte{0x41, 0xf, 0x96, 0xc6}},
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{name: "inst=SETLS/reg=R15", inst: SETLS, dst: RegR15, exp: []byte{0x41, 0xf, 0x96, 0xc7}},
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{name: "inst=SETLT/reg=AX", inst: SETLT, dst: RegAX, exp: []byte{0xf, 0x9c, 0xc0}},
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{name: "inst=SETLT/reg=BX", inst: SETLT, dst: RegBX, exp: []byte{0xf, 0x9c, 0xc3}},
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{name: "inst=SETLT/reg=SP", inst: SETLT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9c, 0xc4}},
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{name: "inst=SETLT/reg=BP", inst: SETLT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9c, 0xc5}},
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{name: "inst=SETLT/reg=SI", inst: SETLT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9c, 0xc6}},
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{name: "inst=SETLT/reg=DI", inst: SETLT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9c, 0xc7}},
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{name: "inst=SETLT/reg=R8", inst: SETLT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9c, 0xc0}},
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{name: "inst=SETLT/reg=R9", inst: SETLT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9c, 0xc1}},
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{name: "inst=SETLT/reg=R13", inst: SETLT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9c, 0xc5}},
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{name: "inst=SETLT/reg=R14", inst: SETLT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9c, 0xc6}},
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{name: "inst=SETLT/reg=R15", inst: SETLT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9c, 0xc7}},
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{name: "inst=SETNE/reg=AX", inst: SETNE, dst: RegAX, exp: []byte{0xf, 0x95, 0xc0}},
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{name: "inst=SETNE/reg=BX", inst: SETNE, dst: RegBX, exp: []byte{0xf, 0x95, 0xc3}},
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{name: "inst=SETNE/reg=SP", inst: SETNE, dst: RegSP, exp: []byte{0x40, 0xf, 0x95, 0xc4}},
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{name: "inst=SETNE/reg=BP", inst: SETNE, dst: RegBP, exp: []byte{0x40, 0xf, 0x95, 0xc5}},
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{name: "inst=SETNE/reg=SI", inst: SETNE, dst: RegSI, exp: []byte{0x40, 0xf, 0x95, 0xc6}},
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{name: "inst=SETNE/reg=DI", inst: SETNE, dst: RegDI, exp: []byte{0x40, 0xf, 0x95, 0xc7}},
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{name: "inst=SETNE/reg=R8", inst: SETNE, dst: RegR8, exp: []byte{0x41, 0xf, 0x95, 0xc0}},
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{name: "inst=SETNE/reg=R9", inst: SETNE, dst: RegR9, exp: []byte{0x41, 0xf, 0x95, 0xc1}},
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{name: "inst=SETNE/reg=R13", inst: SETNE, dst: RegR13, exp: []byte{0x41, 0xf, 0x95, 0xc5}},
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{name: "inst=SETNE/reg=R14", inst: SETNE, dst: RegR14, exp: []byte{0x41, 0xf, 0x95, 0xc6}},
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{name: "inst=SETNE/reg=R15", inst: SETNE, dst: RegR15, exp: []byte{0x41, 0xf, 0x95, 0xc7}},
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{name: "inst=SETPC/reg=AX", inst: SETPC, dst: RegAX, exp: []byte{0xf, 0x9b, 0xc0}},
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{name: "inst=SETPC/reg=BX", inst: SETPC, dst: RegBX, exp: []byte{0xf, 0x9b, 0xc3}},
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{name: "inst=SETPC/reg=SP", inst: SETPC, dst: RegSP, exp: []byte{0x40, 0xf, 0x9b, 0xc4}},
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{name: "inst=SETPC/reg=BP", inst: SETPC, dst: RegBP, exp: []byte{0x40, 0xf, 0x9b, 0xc5}},
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{name: "inst=SETPC/reg=SI", inst: SETPC, dst: RegSI, exp: []byte{0x40, 0xf, 0x9b, 0xc6}},
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{name: "inst=SETPC/reg=DI", inst: SETPC, dst: RegDI, exp: []byte{0x40, 0xf, 0x9b, 0xc7}},
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{name: "inst=SETPC/reg=R8", inst: SETPC, dst: RegR8, exp: []byte{0x41, 0xf, 0x9b, 0xc0}},
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{name: "inst=SETPC/reg=R9", inst: SETPC, dst: RegR9, exp: []byte{0x41, 0xf, 0x9b, 0xc1}},
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{name: "inst=SETPC/reg=R13", inst: SETPC, dst: RegR13, exp: []byte{0x41, 0xf, 0x9b, 0xc5}},
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{name: "inst=SETPC/reg=R14", inst: SETPC, dst: RegR14, exp: []byte{0x41, 0xf, 0x9b, 0xc6}},
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{name: "inst=SETPC/reg=R15", inst: SETPC, dst: RegR15, exp: []byte{0x41, 0xf, 0x9b, 0xc7}},
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{name: "inst=SETPS/reg=AX", inst: SETPS, dst: RegAX, exp: []byte{0xf, 0x9a, 0xc0}},
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{name: "inst=SETPS/reg=BX", inst: SETPS, dst: RegBX, exp: []byte{0xf, 0x9a, 0xc3}},
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{name: "inst=SETPS/reg=SP", inst: SETPS, dst: RegSP, exp: []byte{0x40, 0xf, 0x9a, 0xc4}},
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{name: "inst=SETPS/reg=BP", inst: SETPS, dst: RegBP, exp: []byte{0x40, 0xf, 0x9a, 0xc5}},
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{name: "inst=SETPS/reg=SI", inst: SETPS, dst: RegSI, exp: []byte{0x40, 0xf, 0x9a, 0xc6}},
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{name: "inst=SETPS/reg=DI", inst: SETPS, dst: RegDI, exp: []byte{0x40, 0xf, 0x9a, 0xc7}},
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{name: "inst=SETPS/reg=R8", inst: SETPS, dst: RegR8, exp: []byte{0x41, 0xf, 0x9a, 0xc0}},
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{name: "inst=SETPS/reg=R9", inst: SETPS, dst: RegR9, exp: []byte{0x41, 0xf, 0x9a, 0xc1}},
|
|
{name: "inst=SETPS/reg=R13", inst: SETPS, dst: RegR13, exp: []byte{0x41, 0xf, 0x9a, 0xc5}},
|
|
{name: "inst=SETPS/reg=R14", inst: SETPS, dst: RegR14, exp: []byte{0x41, 0xf, 0x9a, 0xc6}},
|
|
{name: "inst=SETPS/reg=R15", inst: SETPS, dst: RegR15, exp: []byte{0x41, 0xf, 0x9a, 0xc7}},
|
|
{name: "inst=NEGQ/reg=AX", inst: NEGQ, dst: RegAX, exp: []byte{0x48, 0xf7, 0xd8}},
|
|
{name: "inst=NEGQ/reg=BX", inst: NEGQ, dst: RegBX, exp: []byte{0x48, 0xf7, 0xdb}},
|
|
{name: "inst=NEGQ/reg=SP", inst: NEGQ, dst: RegSP, exp: []byte{0x48, 0xf7, 0xdc}},
|
|
{name: "inst=NEGQ/reg=BP", inst: NEGQ, dst: RegBP, exp: []byte{0x48, 0xf7, 0xdd}},
|
|
{name: "inst=NEGQ/reg=SI", inst: NEGQ, dst: RegSI, exp: []byte{0x48, 0xf7, 0xde}},
|
|
{name: "inst=NEGQ/reg=DI", inst: NEGQ, dst: RegDI, exp: []byte{0x48, 0xf7, 0xdf}},
|
|
{name: "inst=NEGQ/reg=R8", inst: NEGQ, dst: RegR8, exp: []byte{0x49, 0xf7, 0xd8}},
|
|
{name: "inst=NEGQ/reg=R9", inst: NEGQ, dst: RegR9, exp: []byte{0x49, 0xf7, 0xd9}},
|
|
{name: "inst=NEGQ/reg=R13", inst: NEGQ, dst: RegR13, exp: []byte{0x49, 0xf7, 0xdd}},
|
|
{name: "inst=NEGQ/reg=R14", inst: NEGQ, dst: RegR14, exp: []byte{0x49, 0xf7, 0xde}},
|
|
{name: "inst=NEGQ/reg=R15", inst: NEGQ, dst: RegR15, exp: []byte{0x49, 0xf7, 0xdf}},
|
|
{name: "inst=INCQ/reg=AX", inst: INCQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc0}},
|
|
{name: "inst=INCQ/reg=BX", inst: INCQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xc3}},
|
|
{name: "inst=INCQ/reg=SP", inst: INCQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xc4}},
|
|
{name: "inst=INCQ/reg=BP", inst: INCQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xc5}},
|
|
{name: "inst=INCQ/reg=SI", inst: INCQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xc6}},
|
|
{name: "inst=INCQ/reg=DI", inst: INCQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xc7}},
|
|
{name: "inst=INCQ/reg=R8", inst: INCQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc0}},
|
|
{name: "inst=INCQ/reg=R9", inst: INCQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc1}},
|
|
{name: "inst=INCQ/reg=R13", inst: INCQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xc5}},
|
|
{name: "inst=INCQ/reg=R14", inst: INCQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xc6}},
|
|
{name: "inst=INCQ/reg=R15", inst: INCQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xc7}},
|
|
{name: "inst=DECQ/reg=AX", inst: DECQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc8}},
|
|
{name: "inst=DECQ/reg=BX", inst: DECQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xcb}},
|
|
{name: "inst=DECQ/reg=SP", inst: DECQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xcc}},
|
|
{name: "inst=DECQ/reg=BP", inst: DECQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xcd}},
|
|
{name: "inst=DECQ/reg=SI", inst: DECQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xce}},
|
|
{name: "inst=DECQ/reg=DI", inst: DECQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xcf}},
|
|
{name: "inst=DECQ/reg=R8", inst: DECQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc8}},
|
|
{name: "inst=DECQ/reg=R9", inst: DECQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc9}},
|
|
{name: "inst=DECQ/reg=R13", inst: DECQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xcd}},
|
|
{name: "inst=DECQ/reg=R14", inst: DECQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xce}},
|
|
{name: "inst=DECQ/reg=R15", inst: DECQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xcf}},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
tc := tc
|
|
a := NewAssembler()
|
|
err := a.encodeNoneToRegister(&nodeImpl{instruction: tc.inst, dstReg: tc.dst})
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, a.buf.Bytes(), tc.name)
|
|
}
|
|
}
|
|
|
|
func TestAssemblerImpl_EncodeNoneToMemory(t *testing.T) {
|
|
t.Run("error", func(t *testing.T) {
|
|
tests := []struct {
|
|
n *nodeImpl
|
|
expErr string
|
|
}{
|
|
{
|
|
n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToMemory, dstReg: RegAX},
|
|
expErr: "ADDL is unsupported for from:none,to:memory type",
|
|
},
|
|
}
|
|
|
|
for _, tt := range tests {
|
|
tc := tt
|
|
t.Run(tc.expErr, func(t *testing.T) {
|
|
tc := tc
|
|
a := NewAssembler()
|
|
err := a.encodeNoneToMemory(tc.n)
|
|
require.EqualError(t, err, tc.expErr)
|
|
})
|
|
}
|
|
})
|
|
|
|
tests := []struct {
|
|
name string
|
|
inst asm.Instruction
|
|
dst asm.Register
|
|
dstOffset int64
|
|
exp []byte
|
|
}{
|
|
{name: "inst=DECQ/reg=AX/offset=0", inst: DECQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x8}},
|
|
{name: "inst=DECQ/reg=AX/offset=1", inst: DECQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x48, 0x1}},
|
|
{name: "inst=DECQ/reg=AX/offset=-1", inst: DECQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x48, 0xff}},
|
|
{name: "inst=DECQ/reg=AX/offset=1243", inst: DECQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=AX/offset=2147483647", inst: DECQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=AX/offset=-32768", inst: DECQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=BX/offset=0", inst: DECQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0xb}},
|
|
{name: "inst=DECQ/reg=BX/offset=1", inst: DECQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4b, 0x1}},
|
|
{name: "inst=DECQ/reg=BX/offset=-1", inst: DECQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4b, 0xff}},
|
|
{name: "inst=DECQ/reg=BX/offset=1243", inst: DECQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8b, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=BX/offset=2147483647", inst: DECQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8b, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=BX/offset=-32768", inst: DECQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8b, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=SP/offset=0", inst: DECQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0xc, 0x24}},
|
|
{name: "inst=DECQ/reg=SP/offset=1", inst: DECQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0x1}},
|
|
{name: "inst=DECQ/reg=SP/offset=-1", inst: DECQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0xff}},
|
|
{name: "inst=DECQ/reg=SP/offset=1243", inst: DECQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=SP/offset=2147483647", inst: DECQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=SP/offset=-32768", inst: DECQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=BP/offset=0", inst: DECQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4d, 0x0}},
|
|
{name: "inst=DECQ/reg=BP/offset=1", inst: DECQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4d, 0x1}},
|
|
{name: "inst=DECQ/reg=BP/offset=-1", inst: DECQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4d, 0xff}},
|
|
{name: "inst=DECQ/reg=BP/offset=1243", inst: DECQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=BP/offset=2147483647", inst: DECQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=BP/offset=-32768", inst: DECQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=SI/offset=0", inst: DECQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xe}},
|
|
{name: "inst=DECQ/reg=SI/offset=1", inst: DECQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4e, 0x1}},
|
|
{name: "inst=DECQ/reg=SI/offset=-1", inst: DECQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4e, 0xff}},
|
|
{name: "inst=DECQ/reg=SI/offset=1243", inst: DECQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=SI/offset=2147483647", inst: DECQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=SI/offset=-32768", inst: DECQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=DI/offset=0", inst: DECQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xf}},
|
|
{name: "inst=DECQ/reg=DI/offset=1", inst: DECQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4f, 0x1}},
|
|
{name: "inst=DECQ/reg=DI/offset=-1", inst: DECQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4f, 0xff}},
|
|
{name: "inst=DECQ/reg=DI/offset=1243", inst: DECQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=DI/offset=2147483647", inst: DECQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=DI/offset=-32768", inst: DECQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=R8/offset=0", inst: DECQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x8}},
|
|
{name: "inst=DECQ/reg=R8/offset=1", inst: DECQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x48, 0x1}},
|
|
{name: "inst=DECQ/reg=R8/offset=-1", inst: DECQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x48, 0xff}},
|
|
{name: "inst=DECQ/reg=R8/offset=1243", inst: DECQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=R8/offset=2147483647", inst: DECQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=R8/offset=-32768", inst: DECQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=R9/offset=0", inst: DECQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x9}},
|
|
{name: "inst=DECQ/reg=R9/offset=1", inst: DECQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x49, 0x1}},
|
|
{name: "inst=DECQ/reg=R9/offset=-1", inst: DECQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x49, 0xff}},
|
|
{name: "inst=DECQ/reg=R9/offset=1243", inst: DECQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x89, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=R9/offset=2147483647", inst: DECQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x89, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=R9/offset=-32768", inst: DECQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x89, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=R13/offset=0", inst: DECQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x4d, 0x0}},
|
|
{name: "inst=DECQ/reg=R13/offset=1", inst: DECQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4d, 0x1}},
|
|
{name: "inst=DECQ/reg=R13/offset=-1", inst: DECQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4d, 0xff}},
|
|
{name: "inst=DECQ/reg=R13/offset=1243", inst: DECQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=R13/offset=2147483647", inst: DECQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=R13/offset=-32768", inst: DECQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=R14/offset=0", inst: DECQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0xe}},
|
|
{name: "inst=DECQ/reg=R14/offset=1", inst: DECQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4e, 0x1}},
|
|
{name: "inst=DECQ/reg=R14/offset=-1", inst: DECQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4e, 0xff}},
|
|
{name: "inst=DECQ/reg=R14/offset=1243", inst: DECQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=R14/offset=2147483647", inst: DECQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=R14/offset=-32768", inst: DECQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=DECQ/reg=R15/offset=0", inst: DECQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0xf}},
|
|
{name: "inst=DECQ/reg=R15/offset=1", inst: DECQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4f, 0x1}},
|
|
{name: "inst=DECQ/reg=R15/offset=-1", inst: DECQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4f, 0xff}},
|
|
{name: "inst=DECQ/reg=R15/offset=1243", inst: DECQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=DECQ/reg=R15/offset=2147483647", inst: DECQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=DECQ/reg=R15/offset=-32768", inst: DECQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=AX/offset=0", inst: INCQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x0}},
|
|
{name: "inst=INCQ/reg=AX/offset=1", inst: INCQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x40, 0x1}},
|
|
{name: "inst=INCQ/reg=AX/offset=-1", inst: INCQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x40, 0xff}},
|
|
{name: "inst=INCQ/reg=AX/offset=1243", inst: INCQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=AX/offset=2147483647", inst: INCQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=AX/offset=-32768", inst: INCQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=BX/offset=0", inst: INCQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x3}},
|
|
{name: "inst=INCQ/reg=BX/offset=1", inst: INCQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x43, 0x1}},
|
|
{name: "inst=INCQ/reg=BX/offset=-1", inst: INCQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x43, 0xff}},
|
|
{name: "inst=INCQ/reg=BX/offset=1243", inst: INCQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x83, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=BX/offset=2147483647", inst: INCQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x83, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=BX/offset=-32768", inst: INCQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x83, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=SP/offset=0", inst: INCQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4, 0x24}},
|
|
{name: "inst=INCQ/reg=SP/offset=1", inst: INCQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0x1}},
|
|
{name: "inst=INCQ/reg=SP/offset=-1", inst: INCQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0xff}},
|
|
{name: "inst=INCQ/reg=SP/offset=1243", inst: INCQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=SP/offset=2147483647", inst: INCQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=SP/offset=-32768", inst: INCQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x84, 0x24, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=BP/offset=0", inst: INCQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x45, 0x0}},
|
|
{name: "inst=INCQ/reg=BP/offset=1", inst: INCQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x45, 0x1}},
|
|
{name: "inst=INCQ/reg=BP/offset=-1", inst: INCQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x45, 0xff}},
|
|
{name: "inst=INCQ/reg=BP/offset=1243", inst: INCQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=BP/offset=2147483647", inst: INCQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=BP/offset=-32768", inst: INCQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=SI/offset=0", inst: INCQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x6}},
|
|
{name: "inst=INCQ/reg=SI/offset=1", inst: INCQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x46, 0x1}},
|
|
{name: "inst=INCQ/reg=SI/offset=-1", inst: INCQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x46, 0xff}},
|
|
{name: "inst=INCQ/reg=SI/offset=1243", inst: INCQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=SI/offset=2147483647", inst: INCQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=SI/offset=-32768", inst: INCQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=DI/offset=0", inst: INCQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x7}},
|
|
{name: "inst=INCQ/reg=DI/offset=1", inst: INCQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x47, 0x1}},
|
|
{name: "inst=INCQ/reg=DI/offset=-1", inst: INCQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x47, 0xff}},
|
|
{name: "inst=INCQ/reg=DI/offset=1243", inst: INCQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=DI/offset=2147483647", inst: INCQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=DI/offset=-32768", inst: INCQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=R8/offset=0", inst: INCQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x0}},
|
|
{name: "inst=INCQ/reg=R8/offset=1", inst: INCQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x40, 0x1}},
|
|
{name: "inst=INCQ/reg=R8/offset=-1", inst: INCQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x40, 0xff}},
|
|
{name: "inst=INCQ/reg=R8/offset=1243", inst: INCQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=R8/offset=2147483647", inst: INCQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=R8/offset=-32768", inst: INCQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=R9/offset=0", inst: INCQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x1}},
|
|
{name: "inst=INCQ/reg=R9/offset=1", inst: INCQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x41, 0x1}},
|
|
{name: "inst=INCQ/reg=R9/offset=-1", inst: INCQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x41, 0xff}},
|
|
{name: "inst=INCQ/reg=R9/offset=1243", inst: INCQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x81, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=R9/offset=2147483647", inst: INCQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x81, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=R9/offset=-32768", inst: INCQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x81, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=R13/offset=0", inst: INCQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x45, 0x0}},
|
|
{name: "inst=INCQ/reg=R13/offset=1", inst: INCQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x45, 0x1}},
|
|
{name: "inst=INCQ/reg=R13/offset=-1", inst: INCQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x45, 0xff}},
|
|
{name: "inst=INCQ/reg=R13/offset=1243", inst: INCQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=R13/offset=2147483647", inst: INCQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=R13/offset=-32768", inst: INCQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=R14/offset=0", inst: INCQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0x6}},
|
|
{name: "inst=INCQ/reg=R14/offset=1", inst: INCQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x46, 0x1}},
|
|
{name: "inst=INCQ/reg=R14/offset=-1", inst: INCQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x46, 0xff}},
|
|
{name: "inst=INCQ/reg=R14/offset=1243", inst: INCQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=R14/offset=2147483647", inst: INCQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=R14/offset=-32768", inst: INCQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=INCQ/reg=R15/offset=0", inst: INCQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0x7}},
|
|
{name: "inst=INCQ/reg=R15/offset=1", inst: INCQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x47, 0x1}},
|
|
{name: "inst=INCQ/reg=R15/offset=-1", inst: INCQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x47, 0xff}},
|
|
{name: "inst=INCQ/reg=R15/offset=1243", inst: INCQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=INCQ/reg=R15/offset=2147483647", inst: INCQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=INCQ/reg=R15/offset=-32768", inst: INCQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=AX/offset=0", inst: JMP, dst: RegAX, dstOffset: 0, exp: []byte{0xff, 0x20}},
|
|
{name: "inst=JMP/reg=AX/offset=1", inst: JMP, dst: RegAX, dstOffset: 1, exp: []byte{0xff, 0x60, 0x1}},
|
|
{name: "inst=JMP/reg=AX/offset=-1", inst: JMP, dst: RegAX, dstOffset: -1, exp: []byte{0xff, 0x60, 0xff}},
|
|
{name: "inst=JMP/reg=AX/offset=1243", inst: JMP, dst: RegAX, dstOffset: 1243, exp: []byte{0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=AX/offset=2147483647", inst: JMP, dst: RegAX, dstOffset: 2147483647, exp: []byte{0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=AX/offset=-32768", inst: JMP, dst: RegAX, dstOffset: -32768, exp: []byte{0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=BX/offset=0", inst: JMP, dst: RegBX, dstOffset: 0, exp: []byte{0xff, 0x23}},
|
|
{name: "inst=JMP/reg=BX/offset=1", inst: JMP, dst: RegBX, dstOffset: 1, exp: []byte{0xff, 0x63, 0x1}},
|
|
{name: "inst=JMP/reg=BX/offset=-1", inst: JMP, dst: RegBX, dstOffset: -1, exp: []byte{0xff, 0x63, 0xff}},
|
|
{name: "inst=JMP/reg=BX/offset=1243", inst: JMP, dst: RegBX, dstOffset: 1243, exp: []byte{0xff, 0xa3, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=BX/offset=2147483647", inst: JMP, dst: RegBX, dstOffset: 2147483647, exp: []byte{0xff, 0xa3, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=BX/offset=-32768", inst: JMP, dst: RegBX, dstOffset: -32768, exp: []byte{0xff, 0xa3, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=SP/offset=0", inst: JMP, dst: RegSP, dstOffset: 0, exp: []byte{0xff, 0x24, 0x24}},
|
|
{name: "inst=JMP/reg=SP/offset=1", inst: JMP, dst: RegSP, dstOffset: 1, exp: []byte{0xff, 0x64, 0x24, 0x1}},
|
|
{name: "inst=JMP/reg=SP/offset=-1", inst: JMP, dst: RegSP, dstOffset: -1, exp: []byte{0xff, 0x64, 0x24, 0xff}},
|
|
{name: "inst=JMP/reg=SP/offset=1243", inst: JMP, dst: RegSP, dstOffset: 1243, exp: []byte{0xff, 0xa4, 0x24, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=SP/offset=2147483647", inst: JMP, dst: RegSP, dstOffset: 2147483647, exp: []byte{0xff, 0xa4, 0x24, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=SP/offset=-32768", inst: JMP, dst: RegSP, dstOffset: -32768, exp: []byte{0xff, 0xa4, 0x24, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=BP/offset=0", inst: JMP, dst: RegBP, dstOffset: 0, exp: []byte{0xff, 0x65, 0x0}},
|
|
{name: "inst=JMP/reg=BP/offset=1", inst: JMP, dst: RegBP, dstOffset: 1, exp: []byte{0xff, 0x65, 0x1}},
|
|
{name: "inst=JMP/reg=BP/offset=-1", inst: JMP, dst: RegBP, dstOffset: -1, exp: []byte{0xff, 0x65, 0xff}},
|
|
{name: "inst=JMP/reg=BP/offset=1243", inst: JMP, dst: RegBP, dstOffset: 1243, exp: []byte{0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=BP/offset=2147483647", inst: JMP, dst: RegBP, dstOffset: 2147483647, exp: []byte{0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=BP/offset=-32768", inst: JMP, dst: RegBP, dstOffset: -32768, exp: []byte{0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=SI/offset=0", inst: JMP, dst: RegSI, dstOffset: 0, exp: []byte{0xff, 0x26}},
|
|
{name: "inst=JMP/reg=SI/offset=1", inst: JMP, dst: RegSI, dstOffset: 1, exp: []byte{0xff, 0x66, 0x1}},
|
|
{name: "inst=JMP/reg=SI/offset=-1", inst: JMP, dst: RegSI, dstOffset: -1, exp: []byte{0xff, 0x66, 0xff}},
|
|
{name: "inst=JMP/reg=SI/offset=1243", inst: JMP, dst: RegSI, dstOffset: 1243, exp: []byte{0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=SI/offset=2147483647", inst: JMP, dst: RegSI, dstOffset: 2147483647, exp: []byte{0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=SI/offset=-32768", inst: JMP, dst: RegSI, dstOffset: -32768, exp: []byte{0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=DI/offset=0", inst: JMP, dst: RegDI, dstOffset: 0, exp: []byte{0xff, 0x27}},
|
|
{name: "inst=JMP/reg=DI/offset=1", inst: JMP, dst: RegDI, dstOffset: 1, exp: []byte{0xff, 0x67, 0x1}},
|
|
{name: "inst=JMP/reg=DI/offset=-1", inst: JMP, dst: RegDI, dstOffset: -1, exp: []byte{0xff, 0x67, 0xff}},
|
|
{name: "inst=JMP/reg=DI/offset=1243", inst: JMP, dst: RegDI, dstOffset: 1243, exp: []byte{0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=DI/offset=2147483647", inst: JMP, dst: RegDI, dstOffset: 2147483647, exp: []byte{0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=DI/offset=-32768", inst: JMP, dst: RegDI, dstOffset: -32768, exp: []byte{0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=R8/offset=0", inst: JMP, dst: RegR8, dstOffset: 0, exp: []byte{0x41, 0xff, 0x20}},
|
|
{name: "inst=JMP/reg=R8/offset=1", inst: JMP, dst: RegR8, dstOffset: 1, exp: []byte{0x41, 0xff, 0x60, 0x1}},
|
|
{name: "inst=JMP/reg=R8/offset=-1", inst: JMP, dst: RegR8, dstOffset: -1, exp: []byte{0x41, 0xff, 0x60, 0xff}},
|
|
{name: "inst=JMP/reg=R8/offset=1243", inst: JMP, dst: RegR8, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=R8/offset=2147483647", inst: JMP, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=R8/offset=-32768", inst: JMP, dst: RegR8, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=R9/offset=0", inst: JMP, dst: RegR9, dstOffset: 0, exp: []byte{0x41, 0xff, 0x21}},
|
|
{name: "inst=JMP/reg=R9/offset=1", inst: JMP, dst: RegR9, dstOffset: 1, exp: []byte{0x41, 0xff, 0x61, 0x1}},
|
|
{name: "inst=JMP/reg=R9/offset=-1", inst: JMP, dst: RegR9, dstOffset: -1, exp: []byte{0x41, 0xff, 0x61, 0xff}},
|
|
{name: "inst=JMP/reg=R9/offset=1243", inst: JMP, dst: RegR9, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa1, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=R9/offset=2147483647", inst: JMP, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa1, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=R9/offset=-32768", inst: JMP, dst: RegR9, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa1, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=R13/offset=0", inst: JMP, dst: RegR13, dstOffset: 0, exp: []byte{0x41, 0xff, 0x65, 0x0}},
|
|
{name: "inst=JMP/reg=R13/offset=1", inst: JMP, dst: RegR13, dstOffset: 1, exp: []byte{0x41, 0xff, 0x65, 0x1}},
|
|
{name: "inst=JMP/reg=R13/offset=-1", inst: JMP, dst: RegR13, dstOffset: -1, exp: []byte{0x41, 0xff, 0x65, 0xff}},
|
|
{name: "inst=JMP/reg=R13/offset=1243", inst: JMP, dst: RegR13, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=R13/offset=2147483647", inst: JMP, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=R13/offset=-32768", inst: JMP, dst: RegR13, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=R14/offset=0", inst: JMP, dst: RegR14, dstOffset: 0, exp: []byte{0x41, 0xff, 0x26}},
|
|
{name: "inst=JMP/reg=R14/offset=1", inst: JMP, dst: RegR14, dstOffset: 1, exp: []byte{0x41, 0xff, 0x66, 0x1}},
|
|
{name: "inst=JMP/reg=R14/offset=-1", inst: JMP, dst: RegR14, dstOffset: -1, exp: []byte{0x41, 0xff, 0x66, 0xff}},
|
|
{name: "inst=JMP/reg=R14/offset=1243", inst: JMP, dst: RegR14, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=R14/offset=2147483647", inst: JMP, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=R14/offset=-32768", inst: JMP, dst: RegR14, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}},
|
|
{name: "inst=JMP/reg=R15/offset=0", inst: JMP, dst: RegR15, dstOffset: 0, exp: []byte{0x41, 0xff, 0x27}},
|
|
{name: "inst=JMP/reg=R15/offset=1", inst: JMP, dst: RegR15, dstOffset: 1, exp: []byte{0x41, 0xff, 0x67, 0x1}},
|
|
{name: "inst=JMP/reg=R15/offset=-1", inst: JMP, dst: RegR15, dstOffset: -1, exp: []byte{0x41, 0xff, 0x67, 0xff}},
|
|
{name: "inst=JMP/reg=R15/offset=1243", inst: JMP, dst: RegR15, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}},
|
|
{name: "inst=JMP/reg=R15/offset=2147483647", inst: JMP, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}},
|
|
{name: "inst=JMP/reg=R15/offset=-32768", inst: JMP, dst: RegR15, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
tc := tc
|
|
a := NewAssembler()
|
|
err := a.encodeNoneToMemory(&nodeImpl{
|
|
types: operandTypesNoneToMemory,
|
|
instruction: tc.inst, dstReg: tc.dst, dstConst: tc.dstOffset,
|
|
})
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, a.buf.Bytes(), tc.name)
|
|
}
|
|
}
|
|
|
|
func TestAssemblerImpl_EncodeRegisterToNone(t *testing.T) {
|
|
t.Run("error", func(t *testing.T) {
|
|
tests := []struct {
|
|
n *nodeImpl
|
|
expErr string
|
|
}{
|
|
{
|
|
n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToNone, srcReg: RegAX},
|
|
expErr: "ADDL is unsupported for from:register,to:none type",
|
|
},
|
|
{
|
|
n: &nodeImpl{instruction: DIVQ, types: operandTypesRegisterToNone},
|
|
expErr: "invalid register [nil]",
|
|
},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
err := a.encodeRegisterToNone(tc.n)
|
|
require.EqualError(t, err, tc.expErr, tc, tc.expErr)
|
|
}
|
|
})
|
|
|
|
tests := []struct {
|
|
name string
|
|
inst asm.Instruction
|
|
reg asm.Register
|
|
exp []byte
|
|
}{
|
|
{name: "DIVL/reg=AX/", reg: RegAX, inst: DIVL, exp: []byte{0xf7, 0xf0}},
|
|
{name: "DIVL/reg=BX/", reg: RegBX, inst: DIVL, exp: []byte{0xf7, 0xf3}},
|
|
{name: "DIVL/reg=SP/", reg: RegSP, inst: DIVL, exp: []byte{0xf7, 0xf4}},
|
|
{name: "DIVL/reg=BP/", reg: RegBP, inst: DIVL, exp: []byte{0xf7, 0xf5}},
|
|
{name: "DIVL/reg=SI/", reg: RegSI, inst: DIVL, exp: []byte{0xf7, 0xf6}},
|
|
{name: "DIVL/reg=DI/", reg: RegDI, inst: DIVL, exp: []byte{0xf7, 0xf7}},
|
|
{name: "DIVL/reg=R8/", reg: RegR8, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf0}},
|
|
{name: "DIVL/reg=R9/", reg: RegR9, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf1}},
|
|
{name: "DIVL/reg=R13/", reg: RegR13, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf5}},
|
|
{name: "DIVL/reg=R14/", reg: RegR14, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf6}},
|
|
{name: "DIVL/reg=R15/", reg: RegR15, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf7}},
|
|
{name: "DIVQ/reg=AX/", reg: RegAX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf0}},
|
|
{name: "DIVQ/reg=BX/", reg: RegBX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf3}},
|
|
{name: "DIVQ/reg=SP/", reg: RegSP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf4}},
|
|
{name: "DIVQ/reg=BP/", reg: RegBP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf5}},
|
|
{name: "DIVQ/reg=SI/", reg: RegSI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf6}},
|
|
{name: "DIVQ/reg=DI/", reg: RegDI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf7}},
|
|
{name: "DIVQ/reg=R8/", reg: RegR8, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf0}},
|
|
{name: "DIVQ/reg=R9/", reg: RegR9, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf1}},
|
|
{name: "DIVQ/reg=R13/", reg: RegR13, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf5}},
|
|
{name: "DIVQ/reg=R14/", reg: RegR14, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf6}},
|
|
{name: "DIVQ/reg=R15/", reg: RegR15, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf7}},
|
|
{name: "IDIVL/reg=AX/", reg: RegAX, inst: IDIVL, exp: []byte{0xf7, 0xf8}},
|
|
{name: "IDIVL/reg=BX/", reg: RegBX, inst: IDIVL, exp: []byte{0xf7, 0xfb}},
|
|
{name: "IDIVL/reg=SP/", reg: RegSP, inst: IDIVL, exp: []byte{0xf7, 0xfc}},
|
|
{name: "IDIVL/reg=BP/", reg: RegBP, inst: IDIVL, exp: []byte{0xf7, 0xfd}},
|
|
{name: "IDIVL/reg=SI/", reg: RegSI, inst: IDIVL, exp: []byte{0xf7, 0xfe}},
|
|
{name: "IDIVL/reg=DI/", reg: RegDI, inst: IDIVL, exp: []byte{0xf7, 0xff}},
|
|
{name: "IDIVL/reg=R8/", reg: RegR8, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf8}},
|
|
{name: "IDIVL/reg=R9/", reg: RegR9, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf9}},
|
|
{name: "IDIVL/reg=R13/", reg: RegR13, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfd}},
|
|
{name: "IDIVL/reg=R14/", reg: RegR14, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfe}},
|
|
{name: "IDIVL/reg=R15/", reg: RegR15, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xff}},
|
|
{name: "IDIVQ/reg=AX/", reg: RegAX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xf8}},
|
|
{name: "IDIVQ/reg=BX/", reg: RegBX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfb}},
|
|
{name: "IDIVQ/reg=SP/", reg: RegSP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfc}},
|
|
{name: "IDIVQ/reg=BP/", reg: RegBP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfd}},
|
|
{name: "IDIVQ/reg=SI/", reg: RegSI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfe}},
|
|
{name: "IDIVQ/reg=DI/", reg: RegDI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xff}},
|
|
{name: "IDIVQ/reg=R8/", reg: RegR8, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf8}},
|
|
{name: "IDIVQ/reg=R9/", reg: RegR9, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf9}},
|
|
{name: "IDIVQ/reg=R13/", reg: RegR13, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfd}},
|
|
{name: "IDIVQ/reg=R14/", reg: RegR14, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfe}},
|
|
{name: "IDIVQ/reg=R15/", reg: RegR15, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xff}},
|
|
{name: "MULL/reg=AX/", reg: RegAX, inst: MULL, exp: []byte{0xf7, 0xe0}},
|
|
{name: "MULL/reg=BX/", reg: RegBX, inst: MULL, exp: []byte{0xf7, 0xe3}},
|
|
{name: "MULL/reg=SP/", reg: RegSP, inst: MULL, exp: []byte{0xf7, 0xe4}},
|
|
{name: "MULL/reg=BP/", reg: RegBP, inst: MULL, exp: []byte{0xf7, 0xe5}},
|
|
{name: "MULL/reg=SI/", reg: RegSI, inst: MULL, exp: []byte{0xf7, 0xe6}},
|
|
{name: "MULL/reg=DI/", reg: RegDI, inst: MULL, exp: []byte{0xf7, 0xe7}},
|
|
{name: "MULL/reg=R8/", reg: RegR8, inst: MULL, exp: []byte{0x41, 0xf7, 0xe0}},
|
|
{name: "MULL/reg=R9/", reg: RegR9, inst: MULL, exp: []byte{0x41, 0xf7, 0xe1}},
|
|
{name: "MULL/reg=R13/", reg: RegR13, inst: MULL, exp: []byte{0x41, 0xf7, 0xe5}},
|
|
{name: "MULL/reg=R14/", reg: RegR14, inst: MULL, exp: []byte{0x41, 0xf7, 0xe6}},
|
|
{name: "MULL/reg=R15/", reg: RegR15, inst: MULL, exp: []byte{0x41, 0xf7, 0xe7}},
|
|
{name: "MULQ/reg=AX/", reg: RegAX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe0}},
|
|
{name: "MULQ/reg=BX/", reg: RegBX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe3}},
|
|
{name: "MULQ/reg=SP/", reg: RegSP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe4}},
|
|
{name: "MULQ/reg=BP/", reg: RegBP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe5}},
|
|
{name: "MULQ/reg=SI/", reg: RegSI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe6}},
|
|
{name: "MULQ/reg=DI/", reg: RegDI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe7}},
|
|
{name: "MULQ/reg=R8/", reg: RegR8, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe0}},
|
|
{name: "MULQ/reg=R9/", reg: RegR9, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe1}},
|
|
{name: "MULQ/reg=R13/", reg: RegR13, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe5}},
|
|
{name: "MULQ/reg=R14/", reg: RegR14, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe6}},
|
|
{name: "MULQ/reg=R15/", reg: RegR15, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe7}},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
err := a.encodeRegisterToNone(&nodeImpl{
|
|
instruction: tc.inst,
|
|
types: operandTypesRegisterToNone, srcReg: tc.reg,
|
|
})
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, a.buf.Bytes(), tc.name)
|
|
}
|
|
}
|
|
|
|
func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
|
|
t.Run("error", func(t *testing.T) {
|
|
tests := []struct {
|
|
n *nodeImpl
|
|
expErr string
|
|
}{
|
|
{
|
|
n: &nodeImpl{instruction: JMP, types: operandTypesRegisterToRegister, srcReg: RegAX, dstReg: RegAX},
|
|
expErr: "JMP is unsupported for from:register,to:register type",
|
|
},
|
|
{
|
|
n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, dstReg: RegAX},
|
|
expErr: "invalid register [nil]",
|
|
},
|
|
{
|
|
n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, srcReg: RegAX},
|
|
expErr: "invalid register [nil]",
|
|
},
|
|
{
|
|
n: &nodeImpl{instruction: MOVL, types: operandTypesRegisterToRegister, srcReg: RegX0, dstReg: RegX1},
|
|
expErr: "MOVL for float to float is undefined",
|
|
},
|
|
}
|
|
|
|
for _, tc := range tests {
|
|
a := NewAssembler()
|
|
err := a.encodeRegisterToRegister(tc.n)
|
|
require.EqualError(t, err, tc.expErr)
|
|
}
|
|
})
|
|
|
|
tests := []struct {
|
|
name string
|
|
n *nodeImpl
|
|
exp []byte
|
|
}{
|
|
{name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0xf3, 0x44, 0xf, 0x6f, 0xd3}},
|
|
{name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0xda}},
|
|
{name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0xf3, 0x45, 0xf, 0x6f, 0xfa}},
|
|
{name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x6f, 0xd3}},
|
|
{name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6f, 0xda}},
|
|
{name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x6f, 0xfa}},
|
|
{name: "PACKSSWB", n: &nodeImpl{instruction: PACKSSWB, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x63, 0xfa}},
|
|
{name: "pmovmskb r15d, xmm10", n: &nodeImpl{instruction: PMOVMSKB, srcReg: RegX10, dstReg: RegR15}, exp: []byte{0x66, 0x45, 0xf, 0xd7, 0xfa}},
|
|
{name: "movmskps eax, xmm10", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x41, 0xf, 0x50, 0xc2}},
|
|
{name: "movmskps r13d, xmm1", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX1, dstReg: RegR13}, exp: []byte{0x44, 0xf, 0x50, 0xe9}},
|
|
{name: "movmskpd eax, xmm10", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x66, 0x41, 0xf, 0x50, 0xc2}},
|
|
{name: "movmskpd r15d, xmm1", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX1, dstReg: RegR15}, exp: []byte{0x66, 0x44, 0xf, 0x50, 0xf9}},
|
|
{name: "pand xmm15, xmm1", n: &nodeImpl{instruction: PAND, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xdb, 0xf9}},
|
|
{name: "por xmm1, xmm15", n: &nodeImpl{instruction: POR, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xeb, 0xcf}},
|
|
{name: "pandn xmm13, xmm15", n: &nodeImpl{instruction: PANDN, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xdf, 0xef}},
|
|
{name: "psrad xmm13, xmm15", n: &nodeImpl{instruction: PSRAD, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xe2, 0xef}},
|
|
{name: "psraw xmm1, xmm1", n: &nodeImpl{instruction: PSRAW, srcReg: RegX1, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xe1, 0xc9}},
|
|
{name: "psrlq xmm14, xmm14", n: &nodeImpl{instruction: PSRLQ, srcReg: RegX14, dstReg: RegX14}, exp: []byte{0x66, 0x45, 0xf, 0xd3, 0xf6}},
|
|
{name: "psrld xmm3, xmm3", n: &nodeImpl{instruction: PSRLD, srcReg: RegX3, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0xd2, 0xdb}},
|
|
{name: "psrlw xmm15, xmm1", n: &nodeImpl{instruction: PSRLW, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xd1, 0xf9}},
|
|
{name: "psllw xmm1, xmm15", n: &nodeImpl{instruction: PSLLW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf1, 0xcf}},
|
|
{name: "punpcklbw xmm1, xmm15", n: &nodeImpl{instruction: PUNPCKLBW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x60, 0xcf}},
|
|
{name: "punpckhbw xmm11, xmm1", n: &nodeImpl{instruction: PUNPCKHBW, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0x68, 0xd9}},
|
|
{name: "pslld xmm11, xmm1", n: &nodeImpl{instruction: PSLLD, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0xf2, 0xd9}},
|
|
{name: "psllq xmm11, xmm15", n: &nodeImpl{instruction: PSLLQ, srcReg: RegX15, dstReg: RegX11}, exp: []byte{0x66, 0x45, 0xf, 0xf3, 0xdf}},
|
|
{
|
|
name: "cmpeqps xmm11, xmm15", n: &nodeImpl{instruction: CMPPS, srcReg: RegX15, dstReg: RegX11, arg: 0}, // CMPPS with arg=0 == Pseudo-Op CMPEQPS.
|
|
exp: []byte{0x45, 0xf, 0xc2, 0xdf, 0x0},
|
|
},
|
|
{
|
|
name: "cmpordps xmm1, xmm5", n: &nodeImpl{instruction: CMPPS, srcReg: RegX5, dstReg: RegX1, arg: 7}, // CMPPS with arg=7 == Pseudo-Op CMPORDPS.
|
|
exp: []byte{0xf, 0xc2, 0xcd, 0x7},
|
|
},
|
|
{name: "cmplepd xmm11, xmm15", n: &nodeImpl{instruction: CMPPD, srcReg: RegX15, dstReg: RegX11, arg: 2}, // CMPPD with arg=2 == Pseudo-Op CMPLEPD.
|
|
exp: []byte{0x66, 0x45, 0xf, 0xc2, 0xdf, 0x2}},
|
|
{
|
|
name: "cmpneqpd xmm1, xmm5", n: &nodeImpl{instruction: CMPPD, srcReg: RegX5, dstReg: RegX1, arg: 4}, // CMPPD with arg=4 == Pseudo-Op CMPNEQPD.
|
|
exp: []byte{0x66, 0xf, 0xc2, 0xcd, 0x4},
|
|
},
|
|
{name: "pcmpgtq xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTQ, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x37, 0xd3}},
|
|
{name: "pcmpgtd xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x66, 0xd3}},
|
|
{name: "pminsd xmm10, xmm3", n: &nodeImpl{instruction: PMINSD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x39, 0xd3}},
|
|
{name: "pmaxsd xmm1, xmm12", n: &nodeImpl{instruction: PMAXSD, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x3d, 0xcc}},
|
|
{name: "pmaxsw xmm1, xmm12", n: &nodeImpl{instruction: PMAXSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xee, 0xcc}},
|
|
{name: "pminsw xmm1, xmm12", n: &nodeImpl{instruction: PMINSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xea, 0xcc}},
|
|
{name: "pcmpgtb xmm1, xmm12", n: &nodeImpl{instruction: PCMPGTB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x64, 0xcc}},
|
|
{name: "pminsb xmm1, xmm12", n: &nodeImpl{instruction: PMINSB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x38, 0xcc}},
|
|
{name: "pmaxsb xmm1, xmm2", n: &nodeImpl{instruction: PMAXSB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3c, 0xca}},
|
|
{name: "pminud xmm1, xmm2", n: &nodeImpl{instruction: PMINUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3b, 0xca}},
|
|
{name: "pminuw xmm1, xmm2", n: &nodeImpl{instruction: PMINUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3a, 0xca}},
|
|
{name: "pminub xmm1, xmm2", n: &nodeImpl{instruction: PMINUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xda, 0xca}},
|
|
{name: "pmaxud xmm1, xmm2", n: &nodeImpl{instruction: PMAXUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3f, 0xca}},
|
|
{name: "pmaxuw xmm1, xmm2", n: &nodeImpl{instruction: PMAXUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3e, 0xca}},
|
|
{name: "pmaxub xmm1, xmm2", n: &nodeImpl{instruction: PMAXUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xde, 0xca}},
|
|
{name: "pcmpgtw xmm1, xmm2", n: &nodeImpl{instruction: PCMPGTW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x65, 0xca}},
|
|
{name: "pmullw xmm13, xmm1", n: &nodeImpl{instruction: PMULLW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd5, 0xe9}},
|
|
{name: "pmulld xmm1, xmm11", n: &nodeImpl{instruction: PMULLD, srcReg: RegX11, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x40, 0xcb}},
|
|
{name: "pmuludq xmm13, xmm1", n: &nodeImpl{instruction: PMULUDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xf4, 0xe9}},
|
|
{name: "psubsb xmm13, xmm1", n: &nodeImpl{instruction: PSUBSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe8, 0xe9}},
|
|
{name: "psubsw xmm13, xmm1", n: &nodeImpl{instruction: PSUBSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe9, 0xe9}},
|
|
{name: "psubusb xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd8, 0xe9}},
|
|
{name: "psubusw xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd9, 0xe9}},
|
|
{name: "paddsw xmm13, xmm1", n: &nodeImpl{instruction: PADDSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xed, 0xe9}},
|
|
{name: "paddsb xmm13, xmm1", n: &nodeImpl{instruction: PADDSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xec, 0xe9}},
|
|
{name: "paddusw xmm13, xmm1", n: &nodeImpl{instruction: PADDUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xdd, 0xe9}},
|
|
{name: "pavgb xmm13, xmm1", n: &nodeImpl{instruction: PAVGB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe0, 0xe9}},
|
|
{name: "pavgw xmm13, xmm1", n: &nodeImpl{instruction: PAVGW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe3, 0xe9}},
|
|
{name: "pabsb xmm13, xmm1", n: &nodeImpl{instruction: PABSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1c, 0xe9}},
|
|
{name: "pabsw xmm13, xmm1", n: &nodeImpl{instruction: PABSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1d, 0xe9}},
|
|
{name: "pabsd xmm13, xmm1", n: &nodeImpl{instruction: PABSD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1e, 0xe9}},
|
|
{name: "blendvpd xmm13, xmm1", n: &nodeImpl{instruction: BLENDVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x15, 0xe9}},
|
|
{name: "maxpd xmm13, xmm1", n: &nodeImpl{instruction: MAXPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5f, 0xe9}},
|
|
{name: "maxps xmm13, xmm1", n: &nodeImpl{instruction: MAXPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5f, 0xe9}},
|
|
{name: "minpd xmm13, xmm1", n: &nodeImpl{instruction: MINPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5d, 0xe9}},
|
|
{name: "minps xmm13, xmm1", n: &nodeImpl{instruction: MINPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5d, 0xe9}},
|
|
{name: "andnpd xmm13, xmm1", n: &nodeImpl{instruction: ANDNPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x55, 0xe9}},
|
|
{name: "andnps xmm13, xmm1", n: &nodeImpl{instruction: ANDNPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x55, 0xe9}},
|
|
{name: "mulps xmm13, xmm1", n: &nodeImpl{instruction: MULPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x59, 0xe9}},
|
|
{name: "mulpd xmm13, xmm1", n: &nodeImpl{instruction: MULPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x59, 0xe9}},
|
|
{name: "divps xmm13, xmm1", n: &nodeImpl{instruction: DIVPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5e, 0xe9}},
|
|
{name: "divpd xmm13, xmm1", n: &nodeImpl{instruction: DIVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5e, 0xe9}},
|
|
{name: "sqrtps xmm13, xmm1", n: &nodeImpl{instruction: SQRTPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x51, 0xe9}},
|
|
{name: "sqrtpd xmm13, xmm1", n: &nodeImpl{instruction: SQRTPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x51, 0xe9}},
|
|
{name: "roundps xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x0}},
|
|
{name: "roundps xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x1}},
|
|
{name: "roundps xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x3}},
|
|
{name: "roundpd xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x0}},
|
|
{name: "roundpd xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x1}},
|
|
{name: "roundpd xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x3}},
|
|
{name: "palignr xmm13, xmm1, 3", n: &nodeImpl{instruction: PALIGNR, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xf, 0xe9, 0x3}},
|
|
{name: "punpcklwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKLWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x61, 0xe9}},
|
|
{name: "punpckhwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKHWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x69, 0xe9}},
|
|
{name: "pmulhuw xmm13, xmm1", n: &nodeImpl{instruction: PMULHUW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe4, 0xe9}},
|
|
{name: "pmuldq xmm13, xmm1", n: &nodeImpl{instruction: PMULDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x28, 0xe9}},
|
|
{name: "pmulhrsw xmm13, xmm1", n: &nodeImpl{instruction: PMULHRSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0xb, 0xe9}},
|
|
{name: "pmovsxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0xea}},
|
|
{name: "pmovsxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0xea}},
|
|
{name: "pmovsxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0xea}},
|
|
{name: "pmovzxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0xea}},
|
|
{name: "pmovzxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0xea}},
|
|
{name: "pmovzxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0xea}},
|
|
{name: "pmulhw xmm2, xmm1", n: &nodeImpl{instruction: PMULHW, srcReg: RegX1, dstReg: RegX2}, exp: []byte{0x66, 0xf, 0xe5, 0xd1}},
|
|
{name: "cmpltps xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPS, srcReg: RegX14, dstReg: RegX1, arg: 1}, exp: []byte{0x41, 0xf, 0xc2, 0xce, 0x1}},
|
|
{name: "cmpunordpd xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPD, srcReg: RegX14, dstReg: RegX1, arg: 3}, exp: []byte{0x66, 0x41, 0xf, 0xc2, 0xce, 0x3}},
|
|
{name: "cvttps2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPS2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0x5b, 0xce}},
|
|
{name: "cvtdq2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5b, 0xce}},
|
|
{name: "movupd xmm1, xmm14", n: &nodeImpl{instruction: MOVUPD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x10, 0xce}},
|
|
{name: "shufps xmm1, xmm14, 5", n: &nodeImpl{instruction: SHUFPS, srcReg: RegX14, dstReg: RegX1, arg: 5}, exp: []byte{0x41, 0xf, 0xc6, 0xce, 0x5}},
|
|
{name: "pmaddwd xmm1, xmm14", n: &nodeImpl{instruction: PMADDWD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf5, 0xce}},
|
|
{name: "cvtdq2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0xe6, 0xce}},
|
|
{name: "unpcklps xmm1, xmm14", n: &nodeImpl{instruction: UNPCKLPS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x14, 0xce}},
|
|
{name: "packuswb xmm1, xmm14", n: &nodeImpl{instruction: PACKUSWB, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x67, 0xce}},
|
|
{name: "packssdw xmm1, xmm14", n: &nodeImpl{instruction: PACKSSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x6b, 0xce}},
|
|
{name: "packusdw xmm1, xmm14", n: &nodeImpl{instruction: PACKUSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x2b, 0xce}},
|
|
{name: "cvtps2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTPS2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5a, 0xce}},
|
|
{name: "cvtpd2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTPD2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x5a, 0xce}},
|
|
{name: "pmaddubsw xmm1, xmm14", n: &nodeImpl{instruction: PMADDUBSW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x4, 0xce}},
|
|
{name: "cvttpd2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPD2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xe6, 0xce}},
|
|
{name: "PADDB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfc, 0xc0}},
|
|
{name: "PADDB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfc, 0xc0}},
|
|
{name: "PADDB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfc, 0xc0}},
|
|
{name: "PADDB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfc, 0xc0}},
|
|
{name: "PADDW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfd, 0xc0}},
|
|
{name: "PADDW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfd, 0xc0}},
|
|
{name: "PADDW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfd, 0xc0}},
|
|
{name: "PADDW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfd, 0xc0}},
|
|
{name: "PADDD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfe, 0xc0}},
|
|
{name: "PADDD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfe, 0xc0}},
|
|
{name: "PADDD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfe, 0xc0}},
|
|
{name: "PADDD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfe, 0xc0}},
|
|
{name: "PADDQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xd4, 0xc0}},
|
|
{name: "PADDQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xd4, 0xc0}},
|
|
{name: "PADDQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xd4, 0xc0}},
|
|
{name: "PADDQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xd4, 0xc0}},
|
|
{name: "ADDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x58, 0xc0}},
|
|
{name: "ADDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x58, 0xc0}},
|
|
{name: "PSUBB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf8, 0xc0}},
|
|
{name: "PSUBB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf8, 0xc0}},
|
|
{name: "PSUBB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf8, 0xc0}},
|
|
{name: "PSUBB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf8, 0xc0}},
|
|
{name: "PSUBW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf9, 0xc0}},
|
|
{name: "PSUBW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf9, 0xc0}},
|
|
{name: "PSUBW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf9, 0xc0}},
|
|
{name: "PSUBW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf9, 0xc0}},
|
|
{name: "PSUBL/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfa, 0xc0}},
|
|
{name: "PSUBL/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfa, 0xc0}},
|
|
{name: "PSUBL/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfa, 0xc0}},
|
|
{name: "PSUBL/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfa, 0xc0}},
|
|
{name: "PSUBQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfb, 0xc0}},
|
|
{name: "PSUBQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfb, 0xc0}},
|
|
{name: "PSUBQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfb, 0xc0}},
|
|
{name: "PSUBQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfb, 0xc0}},
|
|
{name: "SUBPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x5c, 0xc0}},
|
|
{name: "PINSRQ/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRQ/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRQ/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRQ/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRD/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRD/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRD/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRD/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
|
|
{name: "PINSRD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
|
|
{name: "PINSRW/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x1}},
|
|
{name: "PINSRW/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x1}},
|
|
{name: "PINSRW/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x1}},
|
|
{name: "PINSRW/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x1}},
|
|
{name: "PINSRW/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x0}},
|
|
{name: "PINSRW/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x0}},
|
|
{name: "PINSRW/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x0}},
|
|
{name: "PINSRW/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x0}},
|
|
{name: "PINSRB/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
|
|
{name: "PINSRB/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
|
|
{name: "PINSRB/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
|
|
{name: "PINSRB/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
|
|
{name: "PINSRB/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
|
|
{name: "PINSRB/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
|
|
{name: "PINSRB/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
|
|
{name: "PINSRB/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
|
|
{name: "ADDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x1, 0xc0}},
|
|
{name: "ADDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x1, 0xc0}},
|
|
{name: "ADDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x1, 0xc0}},
|
|
{name: "ADDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x1, 0xc0}},
|
|
{name: "ADDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x1, 0xc0}},
|
|
{name: "ADDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x1, 0xc0}},
|
|
{name: "ADDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x1, 0xc0}},
|
|
{name: "ADDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x1, 0xc0}},
|
|
{name: "ADDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x58, 0xc0}},
|
|
{name: "ADDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x58, 0xc0}},
|
|
{name: "ANDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x21, 0xc0}},
|
|
{name: "ANDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x21, 0xc0}},
|
|
{name: "ANDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x21, 0xc0}},
|
|
{name: "ANDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x21, 0xc0}},
|
|
{name: "ANDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x54, 0xc0}},
|
|
{name: "ANDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x54, 0xc0}},
|
|
{name: "ANDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x21, 0xc0}},
|
|
{name: "ANDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x21, 0xc0}},
|
|
{name: "ANDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x21, 0xc0}},
|
|
{name: "ANDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x21, 0xc0}},
|
|
{name: "BSRL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbd, 0xc0}},
|
|
{name: "BSRL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbd, 0xc0}},
|
|
{name: "BSRQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbd, 0xc0}},
|
|
{name: "CMOVQCS/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0x42, 0xc0}},
|
|
{name: "CMOVQCS/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0x42, 0xc0}},
|
|
{name: "CMOVQCS/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0x42, 0xc0}},
|
|
{name: "CMOVQCS/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0x42, 0xc0}},
|
|
{name: "CMPL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x39, 0xc0}},
|
|
{name: "CMPL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0x39, 0xc0}},
|
|
{name: "CMPL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0x39, 0xc0}},
|
|
{name: "CMPL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x39, 0xc0}},
|
|
{name: "CMPQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x39, 0xc0}},
|
|
{name: "CMPQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x39, 0xc0}},
|
|
{name: "CMPQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x39, 0xc0}},
|
|
{name: "CMPQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x39, 0xc0}},
|
|
{name: "COMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2f, 0xc0}},
|
|
{name: "COMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2f, 0xc0}},
|
|
{name: "COMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2f, 0xc0}},
|
|
{name: "CVTSD2SS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSD2SS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSD2SS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSD2SS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSL2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSL2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSQ2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2a, 0xc0}},
|
|
{name: "CVTSS2SD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSS2SD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSS2SD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTSS2SD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5a, 0xc0}},
|
|
{name: "CVTTSD2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSD2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2c, 0xc0}},
|
|
{name: "CVTTSS2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2c, 0xc0}},
|
|
{name: "DIVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5e, 0xc0}},
|
|
{name: "DIVSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5e, 0xc0}},
|
|
{name: "LZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbd, 0xc0}},
|
|
{name: "LZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbd, 0xc0}},
|
|
{name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}},
|
|
{name: "MINSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5d, 0xc0}},
|
|
{name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}},
|
|
{name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}},
|
|
{name: "MINSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5d, 0xc0}},
|
|
{name: "MINSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5d, 0xc0}},
|
|
{name: "MOVBLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVWLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb7, 0xc0}},
|
|
{name: "MOVWLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb7, 0xc0}},
|
|
{name: "MOVWLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb7, 0xc0}},
|
|
{name: "MOVWLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb7, 0xc0}},
|
|
{name: "MOVBLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb6, 0xc0}},
|
|
{name: "MOVBLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb6, 0xc0}},
|
|
{name: "MOVBLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb6, 0xc0}},
|
|
{name: "MOVBLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb6, 0xc0}},
|
|
{name: "MOVBQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVBQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbe, 0xc0}},
|
|
{name: "MOVLQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x63, 0xc0}},
|
|
{name: "MOVLQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x63, 0xc0}},
|
|
{name: "MOVLQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x63, 0xc0}},
|
|
{name: "MOVLQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x63, 0xc0}},
|
|
{name: "MOVL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x89, 0xc0}},
|
|
{name: "MOVL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x89, 0xc0}},
|
|
{name: "MOVL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x89, 0xc0}},
|
|
{name: "MOVL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x89, 0xc0}},
|
|
{name: "MOVL/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVL/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVL/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVL/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x89, 0xc0}},
|
|
{name: "MOVQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x89, 0xc0}},
|
|
{name: "MOVQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x89, 0xc0}},
|
|
{name: "MOVQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x89, 0xc0}},
|
|
{name: "MOVQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x6e, 0xc0}},
|
|
{name: "MOVQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x7e, 0xc0}},
|
|
{name: "MOVWLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbf, 0xc0}},
|
|
{name: "MOVWQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbf, 0xc0}},
|
|
{name: "MULSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x59, 0xc0}},
|
|
{name: "MULSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x59, 0xc0}},
|
|
{name: "IMULQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xaf, 0xc0}},
|
|
{name: "IMULQ/src=DX/dst=AX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegDX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xc2}},
|
|
{name: "IMULQ/src=R10/dst=CX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR10, dstReg: RegCX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xaf, 0xca}},
|
|
{name: "IMULQ/src=CX/dst=DI/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegCX, dstReg: RegDI, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xf9}},
|
|
{name: "ORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x9, 0xc0}},
|
|
{name: "ORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x9, 0xc0}},
|
|
{name: "ORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x9, 0xc0}},
|
|
{name: "ORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x9, 0xc0}},
|
|
{name: "ORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x56, 0xc0}},
|
|
{name: "ORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x56, 0xc0}},
|
|
{name: "ORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x56, 0xc0}},
|
|
{name: "ORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x9, 0xc0}},
|
|
{name: "ORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x9, 0xc0}},
|
|
{name: "ORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x9, 0xc0}},
|
|
{name: "ORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x9, 0xc0}},
|
|
{name: "POPCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xb8, 0xc0}},
|
|
{name: "POPCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xb8, 0xc0}},
|
|
{name: "ROLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc0}},
|
|
{name: "ROLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc0}},
|
|
{name: "ROLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc0}},
|
|
{name: "ROLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc0}},
|
|
{name: "RORL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc8}},
|
|
{name: "RORL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc8}},
|
|
{name: "RORQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc8}},
|
|
{name: "RORQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc8}},
|
|
{name: "ROUNDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
|
|
{name: "ROUNDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
|
|
{name: "ROUNDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
|
|
{name: "ROUNDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
|
|
{name: "ROUNDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
|
|
{name: "ROUNDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
|
|
{name: "ROUNDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
|
|
{name: "ROUNDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
|
|
{name: "ROUNDSD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
|
|
{name: "ROUNDSD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
|
|
{name: "ROUNDSD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
|
|
{name: "ROUNDSD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
|
|
{name: "ROUNDSS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
|
|
{name: "ROUNDSS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
|
|
{name: "ROUNDSS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
|
|
{name: "ROUNDSS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
|
|
{name: "ROUNDSD/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
|
|
{name: "ROUNDSD/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
|
|
{name: "ROUNDSD/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
|
|
{name: "ROUNDSD/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
|
|
{name: "ROUNDSS/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
|
|
{name: "ROUNDSS/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
|
|
{name: "ROUNDSS/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
|
|
{name: "ROUNDSS/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
|
|
{name: "ROUNDSD/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
|
|
{name: "ROUNDSD/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
|
|
{name: "ROUNDSD/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
|
|
{name: "ROUNDSD/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
|
|
{name: "ROUNDSS/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
|
|
{name: "ROUNDSS/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
|
|
{name: "ROUNDSS/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
|
|
{name: "ROUNDSS/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
|
|
{name: "ROUNDSD/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
|
|
{name: "ROUNDSD/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
|
|
{name: "ROUNDSD/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
|
|
{name: "ROUNDSD/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
|
|
{name: "ROUNDSS/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
|
|
{name: "ROUNDSS/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
|
|
{name: "ROUNDSS/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
|
|
{name: "ROUNDSS/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
|
|
{name: "SARL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xf8}},
|
|
{name: "SARL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xf8}},
|
|
{name: "SARQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xf8}},
|
|
{name: "SARQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xf8}},
|
|
{name: "SHLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe0}},
|
|
{name: "SHLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe0}},
|
|
{name: "SHLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe0}},
|
|
{name: "SHLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe0}},
|
|
{name: "SHRL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe8}},
|
|
{name: "SHRL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe8}},
|
|
{name: "SHRQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe8}},
|
|
{name: "SHRQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe8}},
|
|
{name: "SQRTSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x51, 0xc0}},
|
|
{name: "SQRTSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x51, 0xc0}},
|
|
{name: "SUBL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x29, 0xc0}},
|
|
{name: "SUBL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x29, 0xc0}},
|
|
{name: "SUBL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x29, 0xc0}},
|
|
{name: "SUBL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x29, 0xc0}},
|
|
{name: "SUBQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x29, 0xc0}},
|
|
{name: "SUBQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x29, 0xc0}},
|
|
{name: "SUBQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x29, 0xc0}},
|
|
{name: "SUBQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x29, 0xc0}},
|
|
{name: "SUBSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0xc0}},
|
|
{name: "SUBSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5c, 0xc0}},
|
|
{name: "TESTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x85, 0xc0}},
|
|
{name: "TESTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x85, 0xc0}},
|
|
{name: "TESTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x85, 0xc0}},
|
|
{name: "TESTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x85, 0xc0}},
|
|
{name: "TESTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x85, 0xc0}},
|
|
{name: "TESTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x85, 0xc0}},
|
|
{name: "TESTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x85, 0xc0}},
|
|
{name: "TESTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x85, 0xc0}},
|
|
{name: "TZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbc, 0xc0}},
|
|
{name: "TZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbc, 0xc0}},
|
|
{name: "UCOMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2e, 0xc0}},
|
|
{name: "UCOMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2e, 0xc0}},
|
|
{name: "XORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x31, 0xc0}},
|
|
{name: "XORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x31, 0xc0}},
|
|
{name: "XORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x31, 0xc0}},
|
|
{name: "XORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x31, 0xc0}},
|
|
{name: "XORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x57, 0xc0}},
|
|
{name: "XORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x57, 0xc0}},
|
|
{name: "XORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x57, 0xc0}},
|
|
{name: "XORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x31, 0xc0}},
|
|
{name: "XORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x31, 0xc0}},
|
|
{name: "XORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x31, 0xc0}},
|
|
{name: "XORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x31, 0xc0}},
|
|
{name: "XCHGQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x87, 0xc0}},
|
|
{name: "XCHGQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x87, 0xc0}},
|
|
{name: "XCHGQ/src=R8/dst=R9/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR9, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x87, 0xc8}},
|
|
{name: "PXOR/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xef, 0xc0}},
|
|
{name: "PXOR/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xef, 0xc0}},
|
|
{name: "PXOR/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xef, 0xc0}},
|
|
{name: "PSHUFB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x0, 0xc0}},
|
|
{name: "PSHUFB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x0, 0xc0}},
|
|
{name: "PSHUFB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x0, 0xc0}},
|
|
{name: "PSHUFB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x0, 0xc0}},
|
|
{name: "PSHUFD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x0}},
|
|
{name: "PSHUFD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x0}},
|
|
{name: "PSHUFD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x0}},
|
|
{name: "PSHUFD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x0}},
|
|
{name: "PSHUFD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x1}},
|
|
{name: "PSHUFD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x1}},
|
|
{name: "PSHUFD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x1}},
|
|
{name: "PSHUFD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x1}},
|
|
{name: "PEXTRB/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
|
|
{name: "PEXTRB/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
|
|
{name: "PEXTRB/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
|
|
{name: "PEXTRB/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
|
|
{name: "PEXTRW/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc5, 0xc0, 0x1}},
|
|
{name: "PEXTRW/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc5, 0xc0, 0x1}},
|
|
{name: "PEXTRW/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc5, 0xc0, 0x1}},
|
|
{name: "PEXTRW/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc5, 0xc0, 0x1}},
|
|
{name: "PEXTRD/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRD/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRD/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRD/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRQ/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRQ/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRQ/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "PEXTRQ/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
|
|
{name: "MOVLHPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x16, 0xc0}},
|
|
{name: "MOVLHPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x16, 0xc0}},
|
|
{name: "MOVLHPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x16, 0xc0}},
|
|
{name: "MOVLHPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x16, 0xc0}},
|
|
{name: "INSERTPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
|
|
{name: "INSERTPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
|
|
{name: "INSERTPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
|
|
{name: "INSERTPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
|
|
{name: "INSERTPS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
|
|
{name: "INSERTPS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
|
|
{name: "INSERTPS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
|
|
{name: "INSERTPS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
|
|
{name: "PTEST/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x17, 0xc0}},
|
|
{name: "PTEST/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x17, 0xc0}},
|
|
{name: "PTEST/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x17, 0xc0}},
|
|
{name: "PTEST/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x17, 0xc0}},
|
|
{name: "PCMPEQB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x74, 0xc0}},
|
|
{name: "PCMPEQB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x74, 0xc0}},
|
|
{name: "PCMPEQB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x74, 0xc0}},
|
|
{name: "PCMPEQB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x74, 0xc0}},
|
|
{name: "PCMPEQW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x75, 0xc0}},
|
|
{name: "PCMPEQW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x75, 0xc0}},
|
|
{name: "PCMPEQW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x75, 0xc0}},
|
|
{name: "PCMPEQW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x75, 0xc0}},
|
|
{name: "PCMPEQD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x76, 0xc0}},
|
|
{name: "PCMPEQD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x76, 0xc0}},
|
|
{name: "PCMPEQD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x76, 0xc0}},
|
|
{name: "PCMPEQD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x76, 0xc0}},
|
|
{name: "PCMPEQQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x29, 0xc0}},
|
|
{name: "PCMPEQQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x29, 0xc0}},
|
|
{name: "PCMPEQQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x29, 0xc0}},
|
|
{name: "PCMPEQQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x29, 0xc0}},
|
|
{name: "PADDUSB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xdc, 0xc0}},
|
|
{name: "PADDUSB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xdc, 0xc0}},
|
|
{name: "PADDUSB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xdc, 0xc0}},
|
|
{name: "PADDUSB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xdc, 0xc0}},
|
|
{name: "MOVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x10, 0xc0}},
|
|
{name: "MOVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x10, 0xc0}},
|
|
{name: "MOVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x10, 0xc0}},
|
|
{name: "MOVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x10, 0xc0}},
|
|
}
|
|
|
|
for _, tt := range tests {
|
|
tc := tt
|
|
a := NewAssembler()
|
|
err := a.encodeRegisterToRegister(tc.n)
|
|
require.NoError(t, err, tc.name)
|
|
|
|
actual, err := a.Assemble()
|
|
require.NoError(t, err, tc.name)
|
|
require.Equal(t, tc.exp, actual, tc.name)
|
|
}
|
|
}
|