Takeshi Yoneda
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610fdbd664
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wazevo(regalloc): deletes unnecessary kills info (#1813)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-10-23 17:38:28 +09:00 |
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Achille
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f1812c3a1b
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wazevo: optimize regalloc virtual register collections (#1806)
Signed-off-by: Achille Roussel <achille.roussel@gmail.com>
Co-authored-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-10-20 10:07:14 +09:00 |
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Achille
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ff6039a41f
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wazevo: repesent regalloc kills with a bitset (#1804)
Signed-off-by: Achille Roussel <achille.roussel@gmail.com>
Co-authored-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-10-20 09:50:09 +09:00 |
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Achille
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4b6f8f7ccf
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wazevo: add VRegTable data structure (#1802)
Signed-off-by: Achille Roussel <achille.roussel@gmail.com>
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2023-10-19 09:36:56 -07:00 |
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Takeshi Yoneda
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862c9722b6
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wazevo(backend): makes VRegID continuous (#1800)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-10-19 14:12:58 +09:00 |
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Takeshi Yoneda
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9dff143c57
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wazevo(regalloc): reduces map usages (#1787)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-10-16 15:33:32 +09:00 |
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Takeshi Yoneda
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d3e8f79890
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wazevo: adds initial support for SIMD vectors (#1690)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-09-07 11:55:14 +09:00 |
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Takeshi Yoneda
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9e944dcc83
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regalloc: enforces unique definition of virtual regs (#1639)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-08-19 09:04:40 +09:00 |
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Takeshi Yoneda
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02900879bf
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wazevo: initial impl of the new optimizing backend (#1615)
Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
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2023-08-09 10:45:23 +09:00 |
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