wazevo: fuzz, fix f64x2.pmin (#1824)
Signed-off-by: Edoardo Vacchi <evacchi@users.noreply.github.com>
This commit is contained in:
@@ -1102,20 +1102,32 @@ func (m *machine) lowerVMinMaxPseudo(instr *ssa.Instruction, max bool) {
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rn := m.getOperand_NR(m.compiler.ValueDefinition(x), extModeNone)
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rm := m.getOperand_NR(m.compiler.ValueDefinition(y), extModeNone)
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rd := operandNR(m.compiler.VRegOf(instr.Return()))
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creg := m.getOperand_NR(m.compiler.ValueDefinition(instr.Return()), extModeNone)
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tmp := operandNR(m.compiler.AllocateVReg(ssa.TypeV128))
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// creg is overwritten by BSL, so we need to move it to the result register before the instruction
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// in case when it is used somewhere else.
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rd := m.compiler.VRegOf(instr.Return())
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mov := m.allocateInstr()
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mov.asFpuMov128(tmp.nr(), creg.nr())
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m.insert(mov)
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fcmgt := m.allocateInstr()
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if max {
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fcmgt.asVecRRR(vecOpFcmgt, rd, rm, rn, arr)
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fcmgt.asVecRRR(vecOpFcmgt, tmp, rm, rn, arr)
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} else {
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// If min, swap the args.
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fcmgt.asVecRRR(vecOpFcmgt, rd, rn, rm, arr)
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fcmgt.asVecRRR(vecOpFcmgt, tmp, rn, rm, arr)
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}
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m.insert(fcmgt)
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bsl := m.allocateInstr()
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bsl.asVecRRR(vecOpBsl, rd, rm, rn, vecArrangement16B)
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bsl.asVecRRR(vecOpBsl, tmp, rm, rn, vecArrangement16B)
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m.insert(bsl)
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mov2 := m.allocateInstr()
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mov2.asFpuMov128(rd, tmp.nr())
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m.insert(mov2)
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}
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func (m *machine) lowerIRem(execCtxVReg regalloc.VReg, rd, rn, rm operand, _64bit, signed bool) {
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@@ -667,13 +667,13 @@ func Test1817(t *testing.T) {
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})
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}
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// Test1817 tests that i16x8.narrow_i32x4_u assigns the dest register correctly.
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func Test1818(t *testing.T) {
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// Test1820 tests that i16x8.narrow_i32x4_u assigns the dest register correctly.
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func Test1820(t *testing.T) {
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if !platform.CompilerSupported() {
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return
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}
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run(t, func(t *testing.T, r wazero.Runtime) {
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mod, err := r.Instantiate(ctx, getWasmBinary(t, "1818"))
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mod, err := r.Instantiate(ctx, getWasmBinary(t, "1820"))
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require.NoError(t, err)
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m := mod.(*wasm.ModuleInstance)
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_, err = m.ExportedFunction("").Call(ctx)
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@@ -682,3 +682,20 @@ func Test1818(t *testing.T) {
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require.Equal(t, uint64(0xFFFF), m.Globals[1].ValHi)
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})
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}
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// Test1823 tests that f64x2.pmin lowers to BSL with the right register usage
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// (condition register gets overwritten).
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func Test1823(t *testing.T) {
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if !platform.CompilerSupported() {
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return
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}
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run(t, func(t *testing.T, r wazero.Runtime) {
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mod, err := r.Instantiate(ctx, getWasmBinary(t, "1823"))
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require.NoError(t, err)
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m := mod.(*wasm.ModuleInstance)
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_, err = m.ExportedFunction("").Call(ctx)
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require.NoError(t, err)
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require.Equal(t, uint64(17282609607625994159), m.Globals[0].Val)
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require.Equal(t, uint64(4671060543367625455), m.Globals[0].ValHi)
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})
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}
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BIN
internal/integration_test/fuzzcases/testdata/1823.wasm
vendored
Normal file
BIN
internal/integration_test/fuzzcases/testdata/1823.wasm
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Normal file
Binary file not shown.
168
internal/integration_test/fuzzcases/testdata/1823.wat
vendored
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168
internal/integration_test/fuzzcases/testdata/1823.wat
vendored
Normal file
@@ -0,0 +1,168 @@
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(module
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(func (;1;) (result v128 v128 f64 v128 v128 v128 i32 v128 v128 v128 v128 v128)
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v128.const i32x4 0xffffffff 0x0000ffff 0xfefff700 0xffffffff
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v128.const i32x4 0xffffffff 0xffffffff 0x24ffffff 0x10108240
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f64.const -0x1.3e3e3e3e3e3e3p+575 (;=-153732818170537500000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;)
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v128.const i32x4 0x02ffe3e3 0x00e3ff00 0x5151ffff 0x391b5151
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v128.const i32x4 0xe3e34000 0xff10e3e3 0xffff3aff 0x1082f1ff
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v128.const i32x4 0x45ffffff 0x103735c2 0x243a0010 0x0000517f
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i32.const 0
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v128.const i32x4 0xffffff00 0xffffff01 0xffffffff 0x505050ff
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v128.const i32x4 0x00001071 0x00ffffff 0x00000000 0x50505050
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v128.const i32x4 0x50505050 0xff51514e 0xd60001ff 0x10505050
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v128.const i32x4 0x50505050 0x50105050 0x4e505010 0x50105151
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v128.const i32x4 0x50505050 0xffdc1050 0xffffffff 0x000000ff
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)
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(func (;4;)
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(local i32)
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f64.const 0
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call 0
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i32x4.ge_u
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f64x2.pmin
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i16x8.narrow_i32x4_s
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f64x2.pmin
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memory.size
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call 0
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v128.any_true
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call 0
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v128.any_true
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call 0
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i16x8.gt_s
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v128.bitselect
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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i64.reinterpret_f64
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global.get 2
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i64.xor
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global.set 2
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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i64.reinterpret_f64
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global.get 2
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i64.xor
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global.set 2
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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drop
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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i64.reinterpret_f64
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global.get 2
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i64.xor
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global.set 2
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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global.get 1
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i32.xor
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global.set 1
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global.get 0
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v128.xor
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global.set 0
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drop
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global.get 0
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v128.xor
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global.set 0
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i64.reinterpret_f64
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global.get 2
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i64.xor
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global.set 2
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global.get 0
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v128.xor
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global.set 0
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global.get 0
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v128.xor
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global.set 0
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drop
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)
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(table (;0;) 1000 1000 externref)
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(table (;1;) 1000 1000 externref)
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(memory (;0;) 0 0)
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(global (;0;) (mut v128) v128.const i32x4 0x00000000 0x00000000 0x00000000 0x00000000)
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(global (;1;) (mut i32) i32.const 0)
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(global (;2;) (mut i64) i64.const 0)
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(global (;3;) (mut i32) i32.const 1000)
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(export "" (func 1))
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)
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