From 9841c5fc04342dac53bcd4440f9475bc99f031ad Mon Sep 17 00:00:00 2001 From: Edoardo Vacchi Date: Tue, 31 Oct 2023 23:36:28 +0100 Subject: [PATCH] wazevo: fuzz, fix Fcopysign (#1826) Signed-off-by: Edoardo Vacchi --- .../wazevo/backend/isa/arm64/lower_instr.go | 10 +- .../backend/isa/arm64/lower_instr_test.go | 10 +- .../fuzzcases/fuzzcases_test.go | 16 + .../fuzzcases/testdata/1826.wasm | Bin 0 -> 1016 bytes .../fuzzcases/testdata/1826.wat | 359 ++++++++++++++++++ 5 files changed, 389 insertions(+), 6 deletions(-) create mode 100644 internal/integration_test/fuzzcases/testdata/1826.wasm create mode 100644 internal/integration_test/fuzzcases/testdata/1826.wat diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go index 16d8449d..9ed74844 100644 --- a/internal/engine/wazevo/backend/isa/arm64/lower_instr.go +++ b/internal/engine/wazevo/backend/isa/arm64/lower_instr.go @@ -1231,13 +1231,19 @@ func (m *machine) lowerFcopysignImpl(rd, rn, rm, tmpI, tmpF operand, _64bit bool } m.insert(setMSB) + tmpReg := operandNR(m.compiler.AllocateVReg(ssa.TypeF64)) + mov := m.allocateInstr() - mov.asFpuMov64(rd.nr(), rn.nr()) + mov.asFpuMov64(tmpReg.nr(), rn.nr()) m.insert(mov) vbit := m.allocateInstr() - vbit.asVecRRR(vecOpBit, rd, rm, tmpF, vecArrangement8B) + vbit.asVecRRR(vecOpBit, tmpReg, rm, tmpF, vecArrangement8B) m.insert(vbit) + + movDst := m.allocateInstr() + movDst.asFpuMov64(rd.nr(), tmpReg.nr()) + m.insert(movDst) } func (m *machine) lowerBitcast(instr *ssa.Instruction) { diff --git a/internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go b/internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go index e0c32629..eeed0799 100644 --- a/internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go +++ b/internal/engine/wazevo/backend/isa/arm64/lower_instr_test.go @@ -861,8 +861,9 @@ func TestMachine_lowerFcopysign(t *testing.T) { exp: ` movz w1?, #0x8000, lsl 16 ins v2?.s[0], w1? -mov v5?.8b, v3?.8b -bit v5?.8b, v4?.8b, v2?.8b +mov v6?.8b, v3?.8b +bit v6?.8b, v4?.8b, v2?.8b +mov v5?.8b, v6?.8b `, }, { @@ -870,8 +871,9 @@ bit v5?.8b, v4?.8b, v2?.8b exp: ` movz x1?, #0x8000, lsl 48 ins v2?.d[0], x1? -mov v5?.8b, v3?.8b -bit v5?.8b, v4?.8b, v2?.8b +mov v6?.8b, v3?.8b +bit v6?.8b, v4?.8b, v2?.8b +mov v5?.8b, v6?.8b `, }, } { diff --git a/internal/integration_test/fuzzcases/fuzzcases_test.go b/internal/integration_test/fuzzcases/fuzzcases_test.go index 53ad512c..ac6d4cb8 100644 --- a/internal/integration_test/fuzzcases/fuzzcases_test.go +++ b/internal/integration_test/fuzzcases/fuzzcases_test.go @@ -715,3 +715,19 @@ func Test1825(t *testing.T) { require.Equal(t, uint64(18446744073709551615), m.Globals[6].ValHi) }) } + +// Test1825 tests that lowerFcopysignImpl allocates correctly the temporary registers. +func Test1826(t *testing.T) { + if !platform.CompilerSupported() { + return + } + run(t, func(t *testing.T, r wazero.Runtime) { + mod, err := r.Instantiate(ctx, getWasmBinary(t, "1826")) + require.NoError(t, err) + m := mod.(*wasm.ModuleInstance) + _, err = m.ExportedFunction("3").Call(ctx, 0, 0) + require.NoError(t, err) + require.Equal(t, uint64(1608723901141126568), m.Globals[0].Val) + require.Equal(t, uint64(0), m.Globals[0].ValHi) + }) +} diff --git a/internal/integration_test/fuzzcases/testdata/1826.wasm b/internal/integration_test/fuzzcases/testdata/1826.wasm new file mode 100644 index 0000000000000000000000000000000000000000..7c48c2dd6e9cc1b5ecbbe1a2d00f29bdb11a35ee GIT binary patch literal 1016 zcmcgrJ4*vW5T4n+OE7yy6m4P?yz5l({U`)Y&dSPv5VaIHfq+foqY+CXf51ks^9Kl8 zi$x${Yj+^20+K?TbDg`5@iehX;dih*J2T(R?6(~3ln)R9Fv|<9RD}YJR*ouN99NI3 zAqoIIVFFUBVX-1Y+bm%-*-R!T&11}gIKd4N6$~t@^#kH7+)Rq(w4fNyQk^+qI1d~b zz`#WWTtdWU4!FV*S2<&|Gn@|@Xci&$lrYm^8=J;D2;11eea8?r27%>yUP{VZO%jxn zGEe(+U=4@oZ>YeUIvo!0c&e0YG#VfS>pQHiex5O+MER*LN@_(cVs}m3f8BHaPHLWZ-=!EqDVM5-fv!h}o(N<(O1-TqG4e|! z0C8?0R@1n9!!eE56U>c