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wazevo: adds support for DWARF based stack trace (#1734)

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Signed-off-by: Takeshi Yoneda <t.y.mathetake@gmail.com>
This commit is contained in:
Takeshi Yoneda
2023-09-25 10:54:19 +09:00
committed by GitHub
parent 3b8b3fba65
commit 09da2e94b2
16 changed files with 340 additions and 167 deletions
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284
internal/engine/wazevo/backend/isa/arm64/instr.go
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@@ -45,72 +45,73 @@ const (
)
var defKinds = [numInstructionKinds]defKind{
adr: defKindRD,
aluRRR: defKindRD,
aluRRRR: defKindRD,
aluRRImm12: defKindRD,
aluRRBitmaskImm: defKindRD,
aluRRRShift: defKindRD,
aluRRImmShift: defKindRD,
aluRRRExtend: defKindRD,
bitRR: defKindRD,
movZ: defKindRD,
movK: defKindRD,
movN: defKindRD,
mov32: defKindRD,
mov64: defKindRD,
fpuMov64: defKindRD,
fpuMov128: defKindRD,
fpuRR: defKindRD,
fpuRRR: defKindRD,
nop0: defKindNone,
call: defKindCall,
callInd: defKindCall,
ret: defKindNone,
store8: defKindNone,
store16: defKindNone,
store32: defKindNone,
store64: defKindNone,
exitSequence: defKindNone,
condBr: defKindNone,
br: defKindNone,
brTableSequence: defKindNone,
cSet: defKindRD,
extend: defKindRD,
fpuCmp: defKindNone,
uLoad8: defKindRD,
uLoad16: defKindRD,
uLoad32: defKindRD,
sLoad8: defKindRD,
sLoad16: defKindRD,
sLoad32: defKindRD,
uLoad64: defKindRD,
fpuLoad32: defKindRD,
fpuLoad64: defKindRD,
fpuLoad128: defKindRD,
loadFpuConst32: defKindRD,
loadFpuConst64: defKindRD,
loadFpuConst128: defKindRD,
fpuStore32: defKindNone,
fpuStore64: defKindNone,
fpuStore128: defKindNone,
udf: defKindNone,
cSel: defKindRD,
fpuCSel: defKindRD,
movToVec: defKindRD,
movFromVec: defKindRD,
vecDup: defKindRD,
vecExtract: defKindRD,
vecMisc: defKindRD,
vecLanes: defKindRD,
vecShiftImm: defKindRD,
vecPermute: defKindRD,
vecRRR: defKindRD,
fpuToInt: defKindRD,
intToFpu: defKindRD,
cCmpImm: defKindNone,
movToFPSR: defKindNone,
movFromFPSR: defKindRD,
adr: defKindRD,
aluRRR: defKindRD,
aluRRRR: defKindRD,
aluRRImm12: defKindRD,
aluRRBitmaskImm: defKindRD,
aluRRRShift: defKindRD,
aluRRImmShift: defKindRD,
aluRRRExtend: defKindRD,
bitRR: defKindRD,
movZ: defKindRD,
movK: defKindRD,
movN: defKindRD,
mov32: defKindRD,
mov64: defKindRD,
fpuMov64: defKindRD,
fpuMov128: defKindRD,
fpuRR: defKindRD,
fpuRRR: defKindRD,
nop0: defKindNone,
call: defKindCall,
callInd: defKindCall,
ret: defKindNone,
store8: defKindNone,
store16: defKindNone,
store32: defKindNone,
store64: defKindNone,
exitSequence: defKindNone,
condBr: defKindNone,
br: defKindNone,
brTableSequence: defKindNone,
cSet: defKindRD,
extend: defKindRD,
fpuCmp: defKindNone,
uLoad8: defKindRD,
uLoad16: defKindRD,
uLoad32: defKindRD,
sLoad8: defKindRD,
sLoad16: defKindRD,
sLoad32: defKindRD,
uLoad64: defKindRD,
fpuLoad32: defKindRD,
fpuLoad64: defKindRD,
fpuLoad128: defKindRD,
loadFpuConst32: defKindRD,
loadFpuConst64: defKindRD,
loadFpuConst128: defKindRD,
fpuStore32: defKindNone,
fpuStore64: defKindNone,
fpuStore128: defKindNone,
udf: defKindNone,
cSel: defKindRD,
fpuCSel: defKindRD,
movToVec: defKindRD,
movFromVec: defKindRD,
vecDup: defKindRD,
vecExtract: defKindRD,
vecMisc: defKindRD,
vecLanes: defKindRD,
vecShiftImm: defKindRD,
vecPermute: defKindRD,
vecRRR: defKindRD,
fpuToInt: defKindRD,
intToFpu: defKindRD,
cCmpImm: defKindNone,
movToFPSR: defKindNone,
movFromFPSR: defKindRD,
emitSourceOffsetInfo: defKindNone,
}
// defs returns the list of regalloc.VReg that are defined by the instruction.
@@ -156,72 +157,73 @@ const (
)
var useKinds = [numInstructionKinds]useKind{
udf: useKindNone,
aluRRR: useKindRNRM,
aluRRRR: useKindRNRMRA,
aluRRImm12: useKindRN,
aluRRBitmaskImm: useKindRN,
aluRRRShift: useKindRNRM,
aluRRImmShift: useKindRN,
aluRRRExtend: useKindRNRM,
bitRR: useKindRN,
movZ: useKindNone,
movK: useKindNone,
movN: useKindNone,
mov32: useKindRN,
mov64: useKindRN,
fpuMov64: useKindRN,
fpuMov128: useKindRN,
fpuRR: useKindRN,
fpuRRR: useKindRNRM,
nop0: useKindNone,
call: useKindCall,
callInd: useKindCallInd,
ret: useKindRet,
store8: useKindRNAMode,
store16: useKindRNAMode,
store32: useKindRNAMode,
store64: useKindRNAMode,
exitSequence: useKindRN,
condBr: useKindCond,
br: useKindNone,
brTableSequence: useKindRN,
cSet: useKindNone,
extend: useKindRN,
fpuCmp: useKindRNRM,
uLoad8: useKindAMode,
uLoad16: useKindAMode,
uLoad32: useKindAMode,
sLoad8: useKindAMode,
sLoad16: useKindAMode,
sLoad32: useKindAMode,
uLoad64: useKindAMode,
fpuLoad32: useKindAMode,
fpuLoad64: useKindAMode,
fpuLoad128: useKindAMode,
fpuStore32: useKindRNAMode,
fpuStore64: useKindRNAMode,
fpuStore128: useKindRNAMode,
loadFpuConst32: useKindNone,
loadFpuConst64: useKindNone,
loadFpuConst128: useKindNone,
cSel: useKindRNRM,
fpuCSel: useKindRNRM,
movToVec: useKindRN,
movFromVec: useKindRN,
vecDup: useKindRN,
vecExtract: useKindRNRM,
cCmpImm: useKindRN,
vecMisc: useKindRN,
vecLanes: useKindRN,
vecShiftImm: useKindRN,
vecRRR: useKindRNRM,
vecPermute: useKindRNRM,
fpuToInt: useKindRN,
intToFpu: useKindRN,
movToFPSR: useKindRN,
movFromFPSR: useKindNone,
adr: useKindNone,
udf: useKindNone,
aluRRR: useKindRNRM,
aluRRRR: useKindRNRMRA,
aluRRImm12: useKindRN,
aluRRBitmaskImm: useKindRN,
aluRRRShift: useKindRNRM,
aluRRImmShift: useKindRN,
aluRRRExtend: useKindRNRM,
bitRR: useKindRN,
movZ: useKindNone,
movK: useKindNone,
movN: useKindNone,
mov32: useKindRN,
mov64: useKindRN,
fpuMov64: useKindRN,
fpuMov128: useKindRN,
fpuRR: useKindRN,
fpuRRR: useKindRNRM,
nop0: useKindNone,
call: useKindCall,
callInd: useKindCallInd,
ret: useKindRet,
store8: useKindRNAMode,
store16: useKindRNAMode,
store32: useKindRNAMode,
store64: useKindRNAMode,
exitSequence: useKindRN,
condBr: useKindCond,
br: useKindNone,
brTableSequence: useKindRN,
cSet: useKindNone,
extend: useKindRN,
fpuCmp: useKindRNRM,
uLoad8: useKindAMode,
uLoad16: useKindAMode,
uLoad32: useKindAMode,
sLoad8: useKindAMode,
sLoad16: useKindAMode,
sLoad32: useKindAMode,
uLoad64: useKindAMode,
fpuLoad32: useKindAMode,
fpuLoad64: useKindAMode,
fpuLoad128: useKindAMode,
fpuStore32: useKindRNAMode,
fpuStore64: useKindRNAMode,
fpuStore128: useKindRNAMode,
loadFpuConst32: useKindNone,
loadFpuConst64: useKindNone,
loadFpuConst128: useKindNone,
cSel: useKindRNRM,
fpuCSel: useKindRNRM,
movToVec: useKindRN,
movFromVec: useKindRN,
vecDup: useKindRN,
vecExtract: useKindRNRM,
cCmpImm: useKindRN,
vecMisc: useKindRN,
vecLanes: useKindRN,
vecShiftImm: useKindRN,
vecRRR: useKindRNRM,
vecPermute: useKindRNRM,
fpuToInt: useKindRN,
intToFpu: useKindRN,
movToFPSR: useKindRN,
movFromFPSR: useKindNone,
adr: useKindNone,
emitSourceOffsetInfo: useKindNone,
}
// uses returns the list of regalloc.VReg that are used by the instruction.
@@ -1262,6 +1264,8 @@ func (i *instruction) String() (str string) {
str = fmt.Sprintf("exit_sequence %s", formatVRegSized(i.rn.nr(), 64))
case udf:
str = "udf"
case emitSourceOffsetInfo:
str = fmt.Sprintf("source_offset_info %d", ssa.SourceOffset(i.u1))
default:
panic(i.kind)
}
@@ -1434,10 +1438,24 @@ const (
// UDF is the undefined instruction. For debugging only.
udf
// emitSourceOffsetInfo is a dummy instruction to emit source offset info.
// The existence of this instruction does not affect the execution.
emitSourceOffsetInfo
// ------------------- do not define below this line -------------------
numInstructionKinds
)
func (i *instruction) asEmitSourceOffsetInfo(l ssa.SourceOffset) *instruction {
i.kind = emitSourceOffsetInfo
i.u1 = uint64(l)
return i
}
func (i *instruction) sourceOffsetInfo() ssa.SourceOffset {
return ssa.SourceOffset(i.u1)
}
func (i *instruction) asUDF() *instruction {
i.kind = udf
return i
@@ -1971,6 +1989,8 @@ func (i *instruction) size() int64 {
return exitSequenceSize // 5 instructions as in encodeExitSequence.
case nop0:
return 0
case emitSourceOffsetInfo:
return 0
case loadFpuConst32:
if i.u1 == 0 {
return 4 // zero loading can be encoded as a single instruction.